Image Sensor Binning Readout Circuit Parallel Bank Architecture
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Solution Overview
Problem
Conventional image sensors in binning mode suffer from reduced readout speed and degraded image quality due to sequential selection of row lines and column lines, leading to lower signal-to-noise ratio and limited frame rate.
Innovation Solution
An image sensor system that selects row lines in sets and samples signals from column lines using a readout circuit with first and second sampling circuits, averaging signals to produce n×m binning signals, where n and m are natural numbers of 2 or more, to enhance readout speed and signal quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If row lines and column lines are selected one by one in binning mode, then the reading process is simple to implement, but the readout speed is reduced and frame rate is limited
Solution Approach 1:
The pixel array is divided into multiple banks (e.g., four banks) that can be read out simultaneously through parallel column lines. Each bank processes a subset of column lines independently, allowing concurrent readout operations that significantly increase overall readout speed while maintaining manageable complexity through modular organization
Solution Approach 2:
The patent introduces a bank dimension in addition to the traditional row and column dimensions. By organizing pixels into multiple banks with independent column line sets, the system adds a spatial dimension for parallel processing, enabling simultaneous readout from multiple column line groups without increasing the complexity of individual readout paths
2Reliability
If sequential selection of row lines and column lines is used, then the circuit design is straightforward, but the signal-to-noise ratio is reduced and image quality is degraded
Solution Approach 1:
By dividing the pixel array into multiple banks with dedicated column lines, the patent reduces the total number of pixels that need to be read through a single column line set. This segmentation allows for better signal aggregation within each bank while reducing noise accumulation, improving signal-to-noise ratio without requiring a completely new circuit architecture
Solution Approach 2:
The patent merges multiple column line sets into a unified readout structure where signals from multiple banks are combined and processed. This merging approach maintains circuit simplicity by using shared readout circuitry while improving signal-to-noise ratio through the aggregation of signals from multiple parallel paths
3Productivity
If odd-numbered and even-numbered row lines are read out in opposite phase, then the sequential reading process is simple, but time delay is generated between row lines and frame rate cannot be increased
Solution Approach 1:
The patent segments the row lines into multiple groups that can be read out simultaneously through different column line sets. By assigning different row line groups to different banks with independent column lines, the system eliminates the sequential time delay between odd and even row lines, enabling parallel readout that significantly increases frame rate
Solution Approach 2:
The patent implements continuous readout operation by organizing multiple banks to read out different row line groups simultaneously without interruption. This continuous parallel operation eliminates the idle time and phase delays inherent in sequential readout methods, maintaining productive action throughout the entire frame readout period
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the signal-to-noise ratio and frame rate by improving readout speed in binning mode, allowing for higher quality image capture.
Implementation Method 1
each pixel includes a photodiode for converting incident lights into electrical signals
Data Source
AI summary
The present invention provides an image sensor comprising: pixels arranged along a plurality of row lines and column lines in a matrix form; a scan driving unit for selecting the row lines in the unit of n lines in a binning mode; and a read circuit unit for outputting n*m binning signals generated by sampling n*1 signals output in every column line according to the selection of the row lines and averaging the sampled n*1 signals in the unit of m neighboring column lines, wherein each of n and m is a natural number larger than or equal to 2.