3D Image Sensor Layout for TG-FD Capacitance Adjustment
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Solution Overview
Problem
As the number of signal lines increases and pixel pitch becomes finer in solid-state imaging elements with three-dimensional structures, it becomes difficult to adjust the transfer gate (TG) - floating diffusion (FD) capacitance while minimizing the number of wiring layers.
Innovation Solution
A solid-state imaging element with a first semiconductor substrate, a second semiconductor substrate stacked with an insulating layer, a photoelectric conversion element, a floating diffusion layer, a transfer gate, through wires, and an adjustment layer on the second substrate to adjust the capacitance between the transfer gate and floating diffusion layer, facilitating capacitance adjustment without increasing the number of wiring layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If signal lines are drawn out from the first layer to the upper side of the second layer by through contact and arranged in the second and subsequent layers, then the TG-FD capacitance can be optimized in the second and subsequent layers, but the number of wiring layers in the second and subsequent layers increases
Solution Approach 1:
The patent introduces an adjustment layer in the second layer that extends in the column direction (vertical dimension) to adjust TG-FD capacitance, rather than relying solely on horizontal wiring optimization. This dimensional approach allows capacitance adjustment without adding more wiring layers, resolving the contradiction between capacitance optimization and wiring layer complexity
2Measurement precision
If the number of signal lines increases and pixel pitch becomes finer, then the imaging element achieves higher resolution, but the degree of freedom in wiring of the second and subsequent layers decreases
Solution Approach 1:
The adjustment layer extends in the column direction (vertical dimension) rather than being constrained to horizontal routing, providing additional spatial freedom for wiring design. This enables maintaining wiring flexibility even as pixel pitch decreases and signal line density increases
Solution Approach 2:
The adjustment layer is divided into multiple segments that can be independently configured to adjust capacitance for different pixel columns. This segmentation allows flexible wiring design for high-resolution imaging while maintaining ease of manufacture through modular adjustment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables effective adjustment of TG-FD capacitance while maintaining a minimal number of wiring layers, improving the performance and efficiency of the solid-state imaging element.
Implementation Method 1
a photoelectric conversion element that is provided on the first semiconductor substrate and generates charge by photoelectric conversion
Data Source
AI summary
A solid-state imaging element according to an aspect of the present disclosure includes a first semiconductor substrate (11), an insulating layer (46) and a second semiconductor substrate (21), a floating diffusion layer (FD) of the first semiconductor substrate (11), a transfer gate (TG) of the first semiconductor substrate (11), a first through wire (71) electrically connected to the floating diffusion layer (FD) and penetrating the insulating layer (46) and the second semiconductor substrate (21), a second through wire (72) electrically connected to the transfer gate (TG) and penetrating the insulating layer (46) and the second semiconductor substrate (21), a wiring layer (56) stacked on the second semiconductor substrate (21) and having a wiring electrically connected to the first through wire (71) or the second through wire (72), and an adjustment layer that is provided on the second semiconductor substrate (21) so as to be in contact with both or one of the first through wire (71) and the second through wire (72) and adjusts a capacitance between the transfer gate (TG) and the floating diffusion layer (FD).