Image Sensor Floating Diffusion Capacitance for High Dynamic Range
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Solution Overview
Problem
Existing image sensor chips face challenges in achieving a high dynamic range due to insufficient capacitance in image sensors, which limits their ability to store electrical charges generated by varying light intensities.
Innovation Solution
The implementation of parallel-connected metal-insulator-metal (MIM) capacitors in both image sensor and logic circuit structures, utilizing high-k dielectric materials to enhance capacitance, and forming these capacitors in both 2D and 3D configurations within the BEOL metal interconnect layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional capacitor designs are used in image sensors, then device complexity is reduced, but capacitance is insufficient to achieve high dynamic range
Solution Approach 1:
The patent combines multiple capacitors in parallel configuration within the image sensor structure. Specifically, it integrates a first capacitor formed in the semiconductor substrate with a second capacitor formed in the interconnect structure, both connected to the floating diffusion region. This merging of multiple capacitive elements increases the total capacitance value without requiring a single large-capacitance component, thereby achieving high dynamic range while maintaining reasonable device layout.
Solution Approach 2:
The patent transitions from traditional 2D capacitor layouts to 3D vertically-stacked capacitor structures. The capacitors are formed at different vertical levels within the interconnect structure, utilizing the third dimension (vertical stacking) to increase capacitance density. This dimensional transition allows achieving higher capacitance values without proportionally increasing the horizontal footprint area.
2Quantity of substance
If capacitance is increased to achieve high dynamic range, then dynamic range performance is improved, but area occupied by capacitor structures increases
Solution Approach 1:
The patent embeds capacitor structures within the existing interconnect structure layers. The capacitors are nested between metal interconnect layers and dielectric materials, utilizing the vertical space within the existing device architecture. This nesting approach allows the capacitor structures to occupy otherwise unused vertical space, increasing capacitance without significantly expanding the horizontal device footprint.
Solution Approach 2:
The patent employs vertically-stacked capacitor configurations where capacitor plates are arranged at different vertical levels separated by dielectric layers. This 3D stacking approach concentrates capacitance in the vertical dimension rather than spreading it horizontally, thereby achieving high capacitance values with minimal lateral area occupation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the capacitance, enabling the image sensor chips to handle a wide range of light intensities by effectively storing larger electrical charges, thus enhancing their dynamic range performance.
Implementation Method 1
utilizing high-k dielectric materials to enhance capacitance
Data Source
AI summary
A semiconductor device includes an image sensor structure and a periphery device structure. The image sensor structure includes a first semiconductor substrate, a first interconnect structure, a radiation device, a transfer gate transistor electrically coupled to the radiation device, a floating diffusion region electrically coupled to the transfer gate, and a first capacitor disposed in the first interconnect structure. The transfer gate transistor electrically interconnects and disconnects the radiation device and the floating diffusion region. The periphery device structure includes a second interconnect structure disposed on the first interconnect structure, a second semiconductor substrate disposed on the second interconnect structure, a plurality of logic devices disposed in the second semiconductor substrate, and a second capacitor disposed in the second interconnect structure. The first capacitor and the second capacitor are electrically coupled to the floating diffusion region.