Stacked Image Sensor Capacitance Wiring for Wider Dynamic Range

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Solution Overview

Problem

Imaging devices with three-dimensional structures face challenges in extending their dynamic range due to limited capacitance for routing wiring lines, which affects their ability to handle high saturation signal amounts and reduces the signal charge amount.

Innovation Solution

The implementation of capacitance addition wiring lines that are electrically coupled to the conversion efficiency switching transistor, increasing the capacitance of the floating diffusion in the imaging device, allowing it to handle larger signal amounts and extend the dynamic range without increasing the number of wiring lines or production steps.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the pixel size is reduced to increase pixel density, then the imaging device achieves higher resolution, but the capacitance for routing wiring lines becomes limited, reducing the dynamic range

Engineering Contradiction:
Improvepixel densityVSAvoiddynamic range
Core Design Contradiction:
Measurement precisionVSAdaptability or versatility

Solution Approach 1:

The patent introduces a third wiring layer in the vertical dimension to provide additional routing capacity. This third layer is positioned between the first and second wiring layers, allowing wiring lines to be routed in multiple vertical dimensions. By utilizing this additional dimensional space, the patent increases the total capacitance available for signal routing without increasing the horizontal footprint, thereby maintaining dynamic range while supporting reduced pixel sizes and higher pixel density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If capacitance is increased to extend dynamic range, then the imaging device can handle higher signal amounts, but the device complexity and number of wiring lines increases

Engineering Contradiction:
Improvedynamic rangeVSAvoidwiring line configuration
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the wiring structure into three distinct layers, with each layer serving specific routing functions. The first wiring layer handles certain signal routes, the second wiring layer handles other signals, and the third wiring layer (positioned between the first and second) provides additional capacitance and routing capacity. This segmentation allows the patent to increase total capacitance and extend dynamic range while maintaining organized, manageable wiring configurations that do not excessively increase device complexity.

Inventive Principle:
Principle #1Segmentation

3Adaptability or versatility

If more wiring lines are added to increase capacitance, then the dynamic range is extended, but the production steps and manufacturing complexity increase

Engineering Contradiction:
Improvedynamic rangeVSAvoidproduction steps
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent merges the functionality of multiple wiring layers by strategically positioning the third wiring layer between the first and second layers. This intermediate layer is electrically connected to both upper and lower layers through via holes, creating a integrated capacitance network. By merging these layers in this specific configuration, the patent achieves extended dynamic range through increased capacitance while utilizing standard semiconductor manufacturing processes for multi-layer wiring, thereby avoiding excessive increases in production steps and manufacturing complexity.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution enables the imaging device to effectively manage higher signal amounts and maintain a wider dynamic range, even with finer pixel sizes, by adding capacitance to the floating diffusion without increasing production complexity or cost.

Implementation Method 1

the first wiring line and the second wiring line are provided inside the wiring layers formed on the respective opposed surfaces of the first semiconductor substrate including the sensor pixel and the second semiconductor substrate including the readout circuit. This increases the wiring capacitance.

Methodology Applied
Scientific EffectCapacitance: Capacitance

Implementation Method 2

The first semiconductor substrate has a first surface and a second surface and includes a sensor pixel that performs photoelectric conversion

Methodology Applied
Scientific EffectPhotoelectric conversion: Photoelectric Effect

Data Source

PatentEP4068361B1Imaging device and electronic instrument
Publication Date: 2026.02.25 SONY SEMICON SOLUTIONS CORP
  • EP4068361B1 patent drawingFigure 1
  • EP4068361B1 patent drawingFigure 2~3
  • EP4068361B1 patent drawingFigure 4~5

AI summary

An imaging device according to an embodiment of the present disclosure includes: a first semiconductor substrate; a second semiconductor substrate; and a wiring layer. The first semiconductor substrate has a first surface and a second surface and includes a sensor pixel that performs photoelectric conversion. The second semiconductor substrate has a third surface and a fourth surface and includes a readout circuit that outputs a pixel signal based on electric charge outputted from the sensor pixel. The second semiconductor substrate is stacked on the first semiconductor substrate with the first surface and the fourth surface opposed to each other. The wiring layer is provided between the first semiconductor substrate and the second semiconductor substrate and includes a first wiring line and a second wiring line that are electrically coupled to each other. One of the first wiring line and the second wiring line is in an electrically floating state while another of the first wiring line and the second wiring line is electrically coupled to a transistor provided to the first semiconductor substrate or the second semiconductor substrate.