Image Sensor Capacitor Nested Electrodes Charge Loss

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Solution Overview

Problem

Current image sensors face challenges in achieving high performance and efficient global shutter operation, particularly in reducing charge loss and noise generation during image capture.

Innovation Solution

The image sensor design incorporates a semiconductor substrate with a photoelectric conversion layer, transistors, and capacitors, including a unique arrangement of lower electrodes and capacitors to enhance capacitance and reduce noise, allowing for efficient global shutter operation by increasing the surface area and capacitance of the capacitors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the capacitor size is increased to reduce charge loss and noise, then the capacitance and signal quality improve, but the pixel area and device complexity increase

Engineering Contradiction:
Improvecharge loss reductionVSAvoidcapacitor structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The capacitor structure is designed with nested electrodes where a first lower electrode is positioned within a second lower electrode, and an upper electrode is positioned above them. This nested arrangement maximizes the effective capacitance within a confined pixel area, allowing the capacitor to store more charge without proportionally increasing the overall device footprint or structural complexity.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

The capacitor design extends into the vertical dimension by stacking multiple electrodes at different heights (first lower electrode, second lower electrode, and upper electrode) rather than simply expanding the capacitor footprint in the horizontal plane. This three-dimensional electrode arrangement increases capacitance while maintaining a compact pixel layout.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Object-generated harmful factors

If the capacitor surface area is increased to enhance capacitance, then the noise generation is reduced, but the pixel region area occupied increases

Engineering Contradiction:
Improvenoise generationVSAvoidpixel region area
Core Design Contradiction:
Object-generated harmful factorsVSArea of stationary object

Solution Approach 1:

The nested electrode configuration allows the capacitor to achieve increased effective surface area for charge storage without proportionally increasing the projected pixel area. The electrodes are arranged concentrically and vertically, maximizing the capacitance-generating surface while maintaining a compact footprint that fits within the pixel region constraints.

Inventive Principle:
Principle #7Nested doll (Nesting)

Solution Approach 2:

By utilizing the vertical dimension with stacked electrodes at different heights, the capacitor achieves increased effective surface area for noise reduction without expanding the horizontal pixel footprint. The first lower electrode, second lower electrode, and upper electrode are positioned at different vertical levels, creating a three-dimensional capacitance structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design improves shutter efficiency by reducing charge loss and noise generation, enabling high-performance image capture with increased capacitance and improved signal quality.

Implementation Method 1

a photoelectric conversion layer in the semiconductor substrate

Methodology Applied
Scientific EffectPhotoelectric conversion: Photoelectric Effect

Data Source

PatentUS10964740B2Image sensor
Publication Date: 2021.03.30 SAMSUNG ELECTRONICS CO LTD
  • US10964740B2 patent drawing
  • US10964740B2 patent drawing
  • US10964740B2 patent drawing

AI summary

An image sensor includes a semiconductor substrate having a first surface and a second surface opposite to the first surface, a photoelectric conversion layer in the semiconductor substrate, transistors on the first surface of the semiconductor substrate, a first interlayer insulation layer on the transistors, a first lower pad electrode and a second lower pad electrode spaced apart from the first lower pad electrode on the first interlayer insulation layer, a mold insulation layer on the first and second lower pad electrodes, first and second lower electrodes in the mold insulation layer, a dielectric layer on the first and second lower electrodes, an upper electrode on the dielectric layer, and an upper pad electrode connected to the upper electrode and including a different conductive material from the first and second lower pad electrodes. The first lower electrodes are on the first lower pad electrode, and the second lower electrodes are on the second lower pad electrode.