Image Sensor Charge Overflow Control Circuit
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Solution Overview
Problem
Image sensors with charge overflow capabilities face issues due to varying charge overflow integration times across pixel rows, leading to image artifacts and non-linear effects.
Innovation Solution
Implementing a control signal generation circuit that can generate both full and partial assertions of control signals TX and DCG, allowing for simultaneous or sequential pulsing across pixel rows to synchronize charge integration times, and using a multiplexer circuit to manage voltage levels for efficient charge transfer and readout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If charge overflow capabilities are implemented in image pixels, then dynamic range is improved, but image artifacts occur due to varying integration times across pixel rows
Solution Approach 1:
The control signal generation circuit performs preliminary synchronization by asserting control signals TX and DCG simultaneously across all pixel rows before charge integration begins. This preliminary action ensures that all pixels start their overflow charge integration at the same time, preventing the varying integration times that cause image artifacts while maintaining the extended dynamic range provided by charge overflow capabilities.
2Device complexity
If control signals are asserted sequentially across pixel rows, then device complexity is reduced, but charge integration times vary leading to non-linear effects
Solution Approach 1:
The control signal generation circuit is segmented into multiple independent assertion circuits, each capable of independently asserting control signals to different pixel rows. This segmentation allows simultaneous control of multiple rows without increasing overall circuit complexity, as each segment operates autonomously. The segmentation enables synchronized charge integration across all rows while keeping the control architecture manageable and modular.
3Stability of the object's composition
If simultaneous pulsing of control signals is implemented across pixel rows, then charge integration consistency is improved, but control circuit complexity increases
Solution Approach 1:
Multiple control signal assertion functions are merged into a single integrated control signal generation circuit. This circuit combines the capabilities of asserting control signals TX and DCG simultaneously across multiple pixel rows within one unified structure. By merging these functions, the patent achieves synchronized charge integration without proportionally increasing overall circuit complexity, as the merged circuit shares common resources and control logic.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures consistent charge integration times across all pixel rows, mitigating image artifacts and improving image quality by synchronizing the overflow charge integration period.
Implementation Method 1
The pixels in the image sensors may include photosensitive elements such as photodiodes that convert the incoming light into image signals.
Data Source
AI summary
An image sensor may include image pixels arranged in rows and columns. The image pixels may include respective overflow transistors and overflow capacitors and be configured to generate overflow charge during image acquisition. The overflow charge may be generated in a rolling manner on a row-to-row basis by repeatedly activating the overflow transistors and transfer transistors. Row control circuitry may be configured to provide a final synchronous overflow and transfer transistor activation across all of the pixel rows to provide a uniform overflow charge integration time period across all of the pixel rows. Row control circuitry may include a control signal generation circuit configured to generate control signals having full assertions in a first mode and partial assertions for the final synchronous overflow and transfer transistor activation in a second mode.