Image Sensor Chip Stack Structure for Smaller Package Footprints
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in image sensor packages is the increasing size of logic chips relative to image sensor chips, leading to reduced chip die yield and inefficient use of space, as they are typically manufactured in the same size using wafer-to-wafer bonding, which hinders the miniaturization of electronic devices.
Innovation Solution
The image sensor package design features a chip stack structure with a logic chip and image sensor chip of different areas, where the image sensor chip is mounted on the central region of the logic chip, and a dam structure and cover glass are used to protect the image sensor chip, allowing for efficient miniaturization by using chip-to-chip bonding instead of wafer-to-wafer bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wafer-to-wafer bonding is used to manufacture logic chips and image sensor chips in the same size, then manufacturing process simplicity is maintained, but package size increases and chip die yield decreases
Solution Approach 1:
The patent divides the manufacturing process into two separate stages: first manufacturing logic chips on a logic wafer, then manufacturing image sensor chips on a sensor wafer. These separately manufactured chips are subsequently bonded together in a chip-to-chip configuration, allowing each chip type to be optimized independently while reducing overall package size.
Solution Approach 2:
The patent transitions from a planar wafer-to-wafer bonding approach to a three-dimensional chip stacking architecture. By bonding the image sensor chip to the logic chip vertically rather than horizontally, the package footprint is significantly reduced while maintaining all necessary functional connections.
2Ease of manufacture
If wafer-to-wafer bonding is used to manufacture logic chips and image sensor chips in the same size, then manufacturing process simplicity is maintained, but chip die yield decreases
Solution Approach 1:
The patent separates the manufacturing of logic chips and image sensor chips into independent processes on separate wafers. This allows each chip type to be manufactured according to its specific requirements and then bonded together, improving the utilization of the logic wafer area and increasing chip die yield.
Solution Approach 2:
The patent employs asymmetric chip sizing where the logic chip and image sensor chip have different areas, with the image sensor chip being smaller and positioned on the central region of the logic chip. This asymmetric arrangement optimizes space utilization and improves manufacturing efficiency.
3Reliability
If logic chip size increases to accommodate bonding wires, then electrical connectivity is ensured, but package size increases
Solution Approach 1:
The patent moves electrical connections from a horizontal layout (requiring large chip area for bonding wires) to a vertical stacking architecture. The bonding wires are confined to the edge region of the logic chip, while the central region accommodates the smaller image sensor chip, significantly reducing the overall package footprint.
Solution Approach 2:
The patent applies different functional zones to different regions of the logic chip: the central region is optimized for mounting the image sensor chip with minimal bonding wire interference, while the edge region is designated for bonding wire connections. This local differentiation allows compact packaging while maintaining reliable electrical connectivity.
Data Source
AI summary
An image sensor package includes a package substrate, a logic chip mounted on the package substrate and having a central region and an edge region, an image sensor chip mounted on the central region of the logic chip, a bonding wire electrically interconnecting the package substrate to the logic chip and bonded to the edge region of the logic chip, a dam structure disposed in the edge region of the logic chip to cover a portion of the bonding wire, a cover glass disposed on the dam structure, and an encapsulation structure encapsulating the bonding wire on the package substrate.