Image Sensor Circuit Power Reduction via Periodic Switching
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Solution Overview
Problem
Conventional image sensor circuits face challenges in balancing power consumption and footprint, particularly due to the need for constant current flow during ADC conversion and the use of parasitic capacitance for sample holding, which affects noise and efficiency.
Innovation Solution
The image sensor circuit incorporates a column line connected to a sample holding terminal, featuring a light receiving cell with MOS transistors and a sample holding circuit that uses a switch circuit and current source to control voltage sampling and ADC conversion, allowing for reduced power consumption and footprint by optimizing the timing of switch and MOS transistor operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a conventional image sensor circuit uses a source follower and single slope ADC, then the circuit can read pixel signals and perform A/D conversion, but the power consumption increases and the circuit footprint enlarges
Solution Approach 1:
The patent implements periodic action by controlling the current source to operate in alternating phases: during the first period, the current source charges the sampling capacitor while the pixel transistor is on; during the second period, the pixel transistor turns off and the capacitor holds the sampled voltage. This periodic operation allows the circuit to achieve effective A/D conversion while reducing power consumption compared to continuous operation modes.
2Measurement precision
If the number of pixels increases, then the image sensor can capture higher resolution images, but the power consumption and circuit complexity increase
Solution Approach 1:
The patent applies universality by designing a multi-functional circuit where the same current source serves multiple purposes: it acts as a pixel drive current source during the first period and as a sampling capacitor charge source during the second period. The sampling capacitor also functions as both a signal holder and an element in the A/D conversion process. This multi-functionality allows high-resolution imaging without proportionally increasing circuit complexity.
3Area of stationary object
If parasitic capacitance is used for sample holding, then the circuit footprint is reduced, but noise increases and conversion accuracy deteriorates
Solution Approach 1:
The patent extracts the harmful effect of parasitic capacitance by introducing a dedicated sampling capacitor that is explicitly designed and controlled for sample holding purposes. Rather than relying on uncontrolled parasitic capacitance, the invention creates a separate, controlled capacitance element (the sampling capacitor connected to the sample holding terminal) that performs the sample holding function with known and manageable characteristics, thereby reducing noise while maintaining compact footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces power consumption and circuit footprint while maintaining effective sample holding and ADC conversion, minimizing noise and offset voltages, and enabling efficient A/D conversion of light signals.
Implementation Method 1
a light receiving cell including a first MOS transistor M1 that is connected between a power supply VDD and a column line CL and receives an address signal at a gate thereof and a second MOS transistor M2 that is connected in series with the first MOS transistor M1 between the power supply VDD and the column line CL and receives a voltage responsive to received light at a gate thereof
Data Source
AI summary
The controlling circuit of the image censor circuit controls the row decoder to address the light receiving cell with the address signal to turn on the first MOS transistor and turns on the switch circuit with a switch controlling signal, and then controls the row decoder to turn off the first MOS transistor and then turns off the switch circuit with the switch controlling signal.