Image Sensor Clock Buffer Layout for Stable Duty Ratio
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Solution Overview
Problem
Conventional solid-state image sensing apparatuses experience perturbations in the duty ratio of clock signals due to manufacturing variations and increased parasitic capacitance, leading to a decrease in the duty ratio and potential loss of the rectangular waveform of the clock signal as it passes through multiple buffers.
Innovation Solution
The use of a differential circuit in clock buffers, specifically CMOS inverter circuits on even-numbered stages, corrects the duty ratio of the clock signal by employing PMOS and NMOS transistors to maintain a constant duty ratio, preventing perturbations and ensuring the clock signal remains intact throughout the clock supply unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple buffers are used to supply clock signals to counter units, then the clock signal waveform is maintained, but the duty ratio becomes perturbed due to manufacturing variation
Solution Approach 1:
The clock supply unit is divided into multiple independent buffer circuits (first clock buffer, second clock buffer, third clock buffer) that operate in parallel to supply clock signals to different groups of counter units. This segmentation allows each buffer to be optimized independently while maintaining overall system reliability.
Solution Approach 2:
The invention changes the electrical parameters of the buffer circuits by using complementary CMOS technology with specific transistor sizing ratios. The PMOS and NMOS transistors are designed with predetermined width-to-length ratios that compensate for manufacturing variations, thereby stabilizing the duty ratio parameter despite process variations.
2Productivity
If the number of pixels is increased, then the imaging capability is improved, but the clock wiring length and parasitic capacitance increase
Solution Approach 1:
The counter units are divided into multiple groups (first group, second group, third group) that are spatially distributed across the pixel array. Each group is supplied by a dedicated buffer circuit, which segments the clock distribution network and reduces the wiring length from a single centralized source to multiple localized sources.
Solution Approach 2:
The clock signal distribution transitions from a one-dimensional linear expansion to a two-dimensional distributed network. By placing buffers at strategic locations throughout the pixel array and distributing counter units into multiple groups, the clock signal reaches distant pixels through multiple parallel paths rather than a single long wire.
3Volume of moving object
If buffers are miniaturized to reduce device size, then the device compactness is improved, but the duty ratio perturbation increases
Solution Approach 1:
The buffer circuits are designed with predetermined transistor dimension ratios that are optimized to maintain duty ratio stability despite miniaturization. The PMOS and NMOS transistors use specific width-to-length ratios that compensate for scaling effects, allowing the buffers to remain compact while preserving signal integrity.
Solution Approach 2:
The buffer circuit employs complementary CMOS technology that combines PMOS and NMOS transistors in a push-pull configuration. This composite structure leverages the complementary characteristics of the two transistor types to achieve balanced rise and fall times, thereby maintaining duty ratio stability even when the overall device size is reduced.
Data Source
AI summary
A solid-state image sensing apparatus, comprising, a pixel portion, a conversion portion including a first group and a second group each of which includes at least one analog/digital conversion unit to convert an analog signal of the pixel portion into a digital signal, and a clock supply unit including a first clock buffer and a second clock buffer connected in series for propagation of a clock signal, wherein each of the analog/digital conversion units includes a comparison unit and a counter unit, the comparison unit compares the analog signal with a comparison reference potential, the counter unit measures a time from the start of the comparison to the change of the comparison result, each of the first clock buffer and the second clock buffer corrects a duty ratio of a clock signal by using a differential circuit.