Image Sensor Power Reduction via Periodic Clock Buffer Control

The patent implements periodic action by enabling clock buffers only during specific capture periods when data output is required. The master clock is periodically supplied to capture buffers during capture periods, while operation is suspended during non-capture periods. This periodic activation maintains data output accuracy when needed while significantly reducing power consumption by avoiding continuous operation of the buffers.

The patent applies segmentation by dividing the pixel array into multiple banks and the data output circuit into multiple capture buffers. Each buffer is responsible for capturing data from specific banks, allowing selective operation of only the necessary buffers and latches at any given time. This segmentation enables efficient parallel data reading while reducing power consumption by activating only the required segments rather than operating all latches continuously.

The patent implements preliminary action by pre-adjusting the phase of the master clock before data output periods begin. The capture buffers are pre-configured with the appropriate phase relationships needed for accurate data capture. During non-capture periods, the clock phase remains stable without requiring continuous adjustment, eliminating the need for repeated buffer operations at each timing change while maintaining data capture accuracy when output is required.