Image Sensor Clock Buffering for Stable ADC Duty Ratio
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Solution Overview
Problem
Conventional solid-state image sensing apparatuses experience perturbations in the duty ratio of clock signals due to manufacturing variations and increased parasitic capacitance, leading to a shortening of the clock signal's high period and potential disappearance of the rectangular waveform.
Innovation Solution
The implementation of a differential circuit within the clock supply unit, utilizing PMOS and NMOS transistors, corrects the duty ratio of the clock signal by maintaining a constant waveform through buffering stages, preventing perturbations and ensuring the clock signal remains intact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of pixels is increased, then the resolution is improved, but the number of counter units and clock wiring length increase, causing increased parasitic capacitance and perturbation in clock signal duty ratio
Solution Approach 1:
The pixel array is divided into multiple banks (first bank and second bank), with each bank having its own counter units and clock signal paths. This segmentation isolates the parasitic effects to smaller regions, preventing cumulative duty ratio perturbation across the entire array while maintaining high resolution through the combined capacity of multiple banks.
Solution Approach 2:
Clock signal distribution is performed through intermediate buffer circuits and clock signal lines that are carefully designed to minimize parasitic effects. The clock supply unit acts as an intermediary that actively compensates for duty ratio perturbation caused by parasitic capacitance, ensuring stable clock signals reach all counter units despite the large number of pixels.
2Stability of the object's composition
If the number of buffers is increased to supply clock signals, then the clock signal waveform is maintained, but manufacturing variation causes perturbation in the duty ratio of the clock signal
Solution Approach 1:
Multiple buffer circuits are merged into a coordinated clock supply system that operates in unison. The buffers are designed to work together as a unified structure, where the combined effect compensates for individual manufacturing variations, maintaining consistent duty ratio across all clock signal outputs despite variations in individual buffer characteristics.
Solution Approach 2:
The clock signal parameters (voltage levels, timing characteristics) are optimized and adjusted to compensate for manufacturing variations in buffer circuits. By carefully controlling the electrical parameters of the clock signal and buffer operation, the system achieves duty ratio consistency despite variations in physical manufacturing of individual components.
3Area of moving object
If miniaturization is performed to increase pixel density, then the integration is improved, but manufacturing variation and parasitic capacitance cause perturbation in clock signal duty ratio
Solution Approach 1:
Different regions of the pixel array are designed with locally optimized characteristics. Each bank has tailored clock signal distribution and counter unit arrangements that account for local parasitic effects. This local quality optimization ensures that miniaturization benefits are achieved while maintaining duty ratio stability in each specific region, preventing cumulative effects from compromising overall reliability.
Data Source
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AI summary
A solid-state image sensing apparatus, comprising, a pixel portion, a conversion portion including a first group and a second group each of which includes at least one analog/digital conversion unit to convert an analog signal of the pixel portion into a digital signal, and a clock supply unit including a first clock buffer and a second clock buffer connected in series for propagation of a clock signal, wherein each of the analog/digital conversion units includes a comparison unit and a counter unit, the comparison unit compares the analog signal with a comparison reference potential, the counter unit measures a time from the start of the comparison to the change of the comparison result, each of the first clock buffer and the second clock buffer corrects a duty ratio of a clock signal by using a differential circuit.