Image Sensor Clock Chain Segmentation for Depth Measurement

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Solution Overview

Problem

Current image sensors face challenges in stably generating dock signals for depth measurement, particularly in time-of-flight (TOF) schemes, which can lead to errors and noise in depth map generation.

Innovation Solution

The image sensor employs a chain of delay units with selection and buffer circuits to generate forward and backward sequences of delayed clock signals during different exposure phases, using control signals to manage the clock signals and minimize peak current, thereby preventing timing skew and noise.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single clock chain is used to generate dock signals for both phases, then device complexity is reduced, but timing skew and noise occur leading to measurement errors

Engineering Contradiction:
Improveclock chain structureVSAvoiddepth measurement accuracy
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The clock chain is divided into two independent chains: a first clock chain for generating dock signals during the first phase, and a second clock chain for generating dock signals during the second phase. This segmentation allows each chain to operate independently, preventing timing skew and noise that would occur in a shared clock chain, thereby improving depth measurement accuracy while maintaining reasonable device complexity.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If delayed dock signals are generated sequentially along the forward path during the first exposure period, then depth measurement is enabled, but peak current increases causing instability

Engineering Contradiction:
Improvedepth measurement capabilityVSAvoidpeak current consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The system uses periodic exposure periods alternating between a first exposure period (first phase) and a second exposure period (second phase). During the first exposure period, delayed dock signals are generated sequentially along the forward path; during the second exposure period, they are generated sequentially along the backward path. This periodic alternation distributes current consumption over time, preventing excessive peak current while maintaining depth measurement precision.

Inventive Principle:
Principle #19Periodic action

3Measurement precision

If delayed dock signals are generated sequentially along the backward path during the second exposure period, then depth measurement completeness is improved, but timing skew may occur

Engineering Contradiction:
Improvedepth measurement completenessVSAvoidsignal timing consistency
Core Design Contradiction:
Measurement precisionVSStability of the object's composition

Solution Approach 1:

The system employs asymmetric clock chains where the first clock chain generates dock signals along the forward path during the first exposure period, and the second clock chain generates dock signals along the backward path during the second exposure period. This asymmetric design with dedicated chains for each direction ensures that timing relationships are maintained consistently for each path, preventing timing skew while achieving complete depth measurement.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS12167157B2Image sensor and operating method thereof
Publication Date: 2024.12.10 SK HYNIX INC
  • US12167157B2 patent drawing
  • US12167157B2 patent drawing
  • US12167157B2 patent drawing

AI summary

Disclosed is an image sensor including a plurality of selection circuits each suitable for receiving two clock signals among an input clock signal and a plurality of delayed clock signals, and outputting, as each of a plurality of selection clock signals, one selection clock signal between the two clock signals on the basis of a control signal; and a plurality of buffer circuits suitable for generating the plurality of delayed clock signals on the basis of the plurality of selection clock signals outputted from the plurality of selection circuits.