Image Sensor Clock Gating for Power Reduction
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Solution Overview
Problem
Conventional image sensors with digital cores consume excessive power during blanking times when no data is being processed, due to continuously enabled clocks in clock trees and active logic gates.
Innovation Solution
Implementing a power saving technique where clocks for individual blocks in the digital core are dynamically enabled only when processing data, and disabled during blanking times, using timing control delay pipe circuitry to synchronize clock enable signals with data arrival and processing completion in each block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clocks are continuously enabled in the digital core, then data processing can occur without interruption, but power consumption increases during blanking times
Solution Approach 1:
The patent implements dynamic clock gating where clock signals are selectively enabled or disabled based on operational state. During active data processing, clocks are enabled to maintain productivity. During vertical and horizontal blanking intervals when no data processing occurs, clocks are disabled to reduce power consumption. This dynamic switching resolves the contradiction by adapting the clock state to actual processing needs.
Solution Approach 2:
The patent employs periodic clock enablement synchronized with the data processing rhythm. Clocks are enabled during active processing periods and disabled during periodic blanking intervals between data lines and frames. This periodic action pattern allows the system to maintain processing capability when needed while reducing power consumption during natural idle periods, resolving the contradiction between continuous processing and power savings.
2Use of energy by moving object
If clocks are disabled during blanking times, then power consumption is reduced, but data processing may be interrupted
Solution Approach 1:
The patent implements preliminary clock enablement before data arrives at each processing block. Timing control circuitry anticipates the arrival of data and enables clocks in advance, ensuring that processing blocks are ready to process data immediately upon arrival. This preliminary action prevents processing interruptions while allowing clocks to be disabled during actual blanking periods, thus maintaining productivity while reducing power consumption.
Solution Approach 2:
The patent uses feedback from timing control circuitry that monitors data processing state and controls clock enablement accordingly. The system receives feedback about when data is being processed versus when blanking intervals occur, and adjusts clock signals in response. This feedback mechanism ensures clocks are enabled only when needed for processing, preventing interruptions while minimizing power consumption during idle periods.
Data Source
AI summary
Power saving techniques are provided for processing circuitry on image sensors. Processing circuitry may include one or more processing blocks. The processing blocks may receive pixel data in the form of lines separated by blanking time. To reduce power consumption, each processing block may have a clock that is enabled when processing data and disabled during blanking time. The processing blocks may have respective clocks that are enabled and disabled at different times. Timing control circuitry may provide a clock enable signal to a first processing block. Each processing block may receive a clock enable signal and output a time-shifted clock enable signal for a subsequent processing block.