Image Sensor Read Circuit With Local Clock Multipliers
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Solution Overview
Problem
Existing image sensor read circuits face challenges in achieving high acquisition rates without compromising conversion resolution, particularly due to the difficulty in propagating high-frequency clock signals over large distances and the complexity of synchronization mechanisms.
Innovation Solution
A read circuit design that employs a common primary clock with local frequency multipliers to generate secondary clock signals, allowing for increased acquisition rates while maintaining conversion resolution, and utilizes modified natural binary counters to double the counting rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a high-frequency clock signal is propagated over large distances to achieve high acquisition rates, then the acquisition rate increases, but the synchronization complexity and signal integrity deteriorate
Solution Approach 1:
The patent divides the sensor array into multiple blocks, with each block having its own read circuit and frequency multiplier. This segmentation allows independent operation of each block, reducing the complexity of synchronizing a single high-frequency clock across the entire large-distance array while maintaining high acquisition rates locally in each block.
2Productivity
If a high-frequency clock signal is used to achieve high acquisition rates, then the acquisition rate increases, but the power consumption increases
Solution Approach 1:
The patent employs frequency multipliers that generate high-frequency clock signals only when needed for readout operations, rather than continuously propagating high-frequency signals across the entire array. The frequency multiplication is activated selectively based on readout requirements, reducing overall power consumption while maintaining high acquisition rates during active readout.
3Measurement precision
If the conversion resolution is increased to improve image quality, then the conversion resolution improves, but the acquisition rate decreases
Solution Approach 1:
The patent implements dynamic control of the readout process where the frequency multiplier dynamically adjusts the clock frequency based on the number of pixels to be read and the desired acquisition rate. This dynamic adjustment allows the system to optimize between conversion resolution and acquisition rate by adapting the readout speed to the specific operational requirements, rather than being constrained by a fixed high-frequency clock.
Data Source
AI summary
A circuit for reading a pixel matrix array comprises, for each column of pixels of the matrix array: voltage-to-delay converting circuits receiving, on an input, a voltage value representative of the voltage of a read conductor of a respective column of pixels of the matrix array and delivering as output a binary signal called a comparative signal, this signal switched at a time dependent on the input voltage value; frequency-multiplying circuits, one for each of the voltage-to-delay converting circuits, receiving as input a primary clock signal and delivering as output secondary clock signals of multiplied frequency; and binary counters, receiving, on a first input, a the secondary clock signal, and, on a second input, a the binary comparative signal and counting at a rate dictated by the secondary clock signal until the binary comparative signal switches. An image sensor comprising a matrix array of pixels, in particular active pixels, and a read circuit is also provided.