Image Sensor Column Readout Lines with Multiple ADCs

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Solution Overview

Problem

Current image sensor circuits face limitations in processing speed and image quality, particularly in industrial applications, where faster data acquisition and better image resolution are demanded.

Innovation Solution

The implementation of an image sensor circuit architecture that includes multiple analog-to-digital conversion (ADC) circuits per column and allows simultaneous activation of two rows of pixel circuits to output analog signals to column readout lines, enabling faster data processing and improved image quality through parallel processing and reduced propagation delays.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional single readout line per column is used, then device complexity is reduced, but processing speed and data rate are limited

Engineering Contradiction:
Improveprocessing speedVSAvoiddevice complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The patent divides each column's readout path into multiple parallel readout lines (e.g., first readout line and second readout line per column). This segmentation allows multiple pixel rows to be read out simultaneously through different paths, thereby increasing processing speed and data rate without requiring a complete redesign of the entire sensor architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces an additional dimension to the readout architecture by adding multiple readout lines per column. This transforms the traditional single-path readout into a multi-path parallel readout system, enabling simultaneous readout of multiple pixel rows and significantly improving data throughput.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If multiple rows are activated simultaneously, then productivity increases, but propagation delay increases

Engineering Contradiction:
Improvedata acquisition rateVSAvoidpropagation delay
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

By segmenting the readout paths into multiple parallel lines, the patent enables simultaneous activation of multiple pixel rows without causing signal congestion. Each readout line handles a specific subset of pixels, maintaining signal integrity and minimizing propagation delay even when multiple rows are active simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces column selection circuits and readout line selection mechanisms that act as intermediaries to manage the simultaneous readout of multiple pixel rows. These intermediary components route signals from different pixel rows to appropriate readout lines, coordinating the readout process to minimize propagation delay while maximizing data acquisition rate.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If multiple ADC circuits per column are implemented, then data rate increases, but device complexity increases

Engineering Contradiction:
Improvedata rateVSAvoiddevice complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent divides the ADC resources into multiple circuits per column, with each ADC circuit handling a specific subset of pixel data. This segmentation enables parallel conversion of analog pixel signals to digital data, increasing the overall data rate. The modular structure allows for systematic integration and management of multiple ADC circuits.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent designs the multiple ADC circuits per column to handle different pixel rows or different data streams simultaneously. Each ADC circuit is configured to perform the same conversion function but operates on different input signals, providing multi-functionality that increases data throughput without requiring fundamentally different circuit designs.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7488928B2Image sensor circuits and methods with multiple readout lines per column of pixel circuits
Publication Date: 2009.02.10 ALEXANDER KRYMSKI D B A ALEXIMA
  • US7488928B2 patent drawing
  • US7488928B2 patent drawing
  • US7488928B2 patent drawing

AI summary

An image sensor circuit of various embodiments includes a pixel array with a plurality of pixel circuits arranged in a plurality of rows and a plurality of columns. Each column of the pixel array includes a corresponding first set of pixel circuits connected to output analog pixel signals to a respective first column readout line, and a corresponding second set of pixel circuits connected to output analog pixel signals to a respective second column readout line. Two or more analog-to-digital conversion circuits may be provided for each column of pixel circuits in the pixel array, and two or more rows of pixel circuits in the pixel array may be activated to output analog pixel signals to corresponding column readout lines at a same time.