Image Sensor Comparator Circuit for Parasitic Capacitance Control
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Solution Overview
Problem
Conventional solid-state image sensors with single-slope ADCs face issues with image quality due to increased parasitic capacitance in differential transistors, leading to errors in comparison timing and deteriorated image data when the difference between reset and signal levels is large.
Innovation Solution
Incorporating a voltage divider circuit, input and output differential transistors, and a control transistor to reduce the gate-source voltage of differential transistors, along with current mirror transistors and resistors, to manage parasitic capacitance and improve image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a voltage divider circuit is added to reduce power supply voltage and power consumption, then power consumption is reduced, but the gate-source voltage of the differential transistor increases, causing increased parasitic capacitance and errors in comparison timing
Solution Approach 1:
A control transistor is introduced as an intermediary element between the voltage divider circuit and the differential transistor. This control transistor actively regulates the gate-source voltage of the differential transistor, preventing it from increasing excessively even when the power supply voltage is reduced by the voltage divider circuit. By mediating the voltage relationship, the control transistor maintains stable parasitic capacitance and accurate comparison timing while allowing the voltage divider to achieve its power reduction goal.
2Loss of energy
If the power supply voltage is reduced by the voltage divider circuit, then power consumption is reduced, but image quality deteriorates due to increased parasitic capacitance
Solution Approach 1:
The control transistor serves as a mediator that protects the image quality from deterioration. It actively manages the gate-source voltage of the differential transistor to maintain stable parasitic capacitance values, ensuring that comparison timing remains accurate and image data quality is preserved even when operating with reduced power supply voltage from the voltage divider circuit.
3Adaptability or versatility
If the gate-source voltage of the differential transistor increases, then the voltage difference between reset and signal levels is handled, but parasitic capacitance increases causing errors in inversion timing
Solution Approach 1:
The control transistor implements a feedback mechanism where its gate voltage is controlled based on the output from the voltage divider circuit, and it actively adjusts its own operation to maintain the gate-source voltage of the differential transistor within an optimal range. This feedback control ensures that even when handling large voltage differences between reset and signal levels, the parasitic capacitance remains stable and inversion timing accuracy is maintained.
Data Source
AI summary
In a solid-state image sensor provided with a comparator that compares a reference signal and a pixel signal, the image quality of image data is improved.A voltage divider circuit supplies a divided voltage of an input voltage and a predetermined reference voltage that are input. An input-side differential transistor outputs a drain current corresponding to the gate-source voltage between the divided voltage input to the gate and a predetermined source voltage. An output-side differential transistor outputs a voltage corresponding to the drain current as a result of comparison between the input voltage and the reference voltage. A control transistor reduces the gate-source voltage in a case where the input voltage is out of a predetermined range.