Image Sensor A/D Comparator with Limiter for Noise Reduction
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Solution Overview
Problem
Current CMOS image sensors face challenges in reducing noise and power consumption while maintaining high image quality, particularly due to limitations in analog-to-digital (A/D) converters using correlated double sampling (CDS) technology.
Innovation Solution
The implementation of a comparison circuit with a first comparator stage, a limiter, and a second comparator stage in the A/D converter, which includes an n-type transistor to limit voltage levels and prevent column fixed pattern noise, along with a counter to generate digital signals based on comparison result signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a conventional A/D converter using CDS technology is used, then image quality can be maintained, but noise and power consumption cannot be effectively reduced
Solution Approach 1:
The comparison circuit is divided into two distinct stages: a first comparator stage for initial comparison and a second comparator stage for final comparison result generation. This segmentation allows each stage to be optimized independently, with the first stage handling coarse comparison and the second stage providing refined results, thereby reducing overall power consumption while maintaining image quality.
Solution Approach 2:
A limiter circuit is introduced as an intermediary component between the first and second comparator stages. The limiter shapes the output signal from the first comparator stage before it is fed to the second comparator stage, ensuring optimal signal levels and reducing noise propagation. This intermediary function enables effective noise reduction while maintaining the reliability of the final comparison result.
2Object-affected harmful factors
If noise reduction techniques are applied in the A/D converter, then image quality improves, but device complexity increases
Solution Approach 1:
The comparison circuit is divided into two distinct stages: a first comparator stage for initial comparison and a second comparator stage for final comparison result generation. This segmentation allows each stage to be optimized independently, with the first stage handling coarse comparison and the second stage providing refined results, thereby reducing overall power consumption while maintaining image quality.
Solution Approach 2:
A limiter circuit is introduced as an intermediary component between the first and second comparator stages. The limiter shapes the output signal from the first comparator stage before it is fed to the second comparator stage, ensuring optimal signal levels and reducing noise propagation. This intermediary function enables effective noise reduction while maintaining the reliability of the final comparison result.
3Use of energy by moving object
If power consumption is reduced in the A/D converter, then energy efficiency improves, but measurement precision may deteriorate
Solution Approach 1:
The comparison circuit is divided into two distinct stages: a first comparator stage for initial comparison and a second comparator stage for final comparison result generation. This segmentation allows each stage to be optimized independently, with the first stage handling coarse comparison and the second stage providing refined results, thereby reducing overall power consumption while maintaining image quality.
Solution Approach 2:
The limiter circuit modifies the voltage parameters of the signal from the first comparator stage by clamping it to specific voltage levels. This parameter change ensures that the signal presented to the second comparator stage is within the optimal operating range, maintaining measurement precision while allowing the first stage to operate at lower power levels.
Data Source
AI summary
An A/D converter and an image sensor are disclosed. The image sensor includes: a pixel array including a plurality of pixels; a ramp signal generator configured to generate a ramp signal; and a comparison circuit configured to output a comparison result signal by comparing a pixel signal output by the pixel array with the ramp signal. The comparison circuit includes: a first comparator stage configured to output a first stage output signal according to a result of comparing the pixel signal with the ramp signal, to a first circuit node; a limiter including an n-type transistor having one end connected to the first circuit node and an opposite end to which power supply voltage is applied; and a second comparator stage configured to generate the comparison result signal by shaping the first stage output signal.


