Image Sensor Comparator Circuit for Streaking Suppression
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Solution Overview
Problem
Conventional solid-state image pickup devices suffer from image quality deterioration due to 'streaking' caused by fluctuations in the reference signal during AD conversion, especially in regions with large brightness differences, leading to increased noise and reduced resolution.
Innovation Solution
The design incorporates a comparator with a specific transistor configuration, including differential transistors, load transistors, and a current source transistor, where the ratios of their gate widths to gate lengths are optimized to reduce capacitance and current fluctuations, and the addition of resistance components or switch elements to manage voltage drops, thereby suppressing streaking without compromising noise characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the gate width/gate length ratio of the first differential transistor is increased to reduce temporal fluctuation, then noise characteristics are improved, but the capacitance increases causing streaking
Solution Approach 1:
The patent applies asymmetry by setting different gate width/gate length ratios for the first and second differential transistors. Specifically, the first differential transistor (connected to reference signal) has a larger W/L ratio than the second differential transistor (connected to pixel signal). This asymmetric design allows the first transistor to have higher capacitance for reducing temporal fluctuation and noise, while the second transistor maintains lower capacitance to prevent streaking in the pixel signal path.
2Measurement precision
If the gate width/gate length ratio of the second differential transistor is increased to reduce temporal fluctuation, then noise characteristics are improved, but the capacitance increases causing streaking
Solution Approach 1:
The patent applies asymmetry by setting different gate width/gate length ratios for the first and second differential transistors. Specifically, the first differential transistor (connected to reference signal) has a larger W/L ratio than the second differential transistor (connected to pixel signal). This asymmetric design allows the first transistor to have higher capacitance for reducing temporal fluctuation and noise, while the second transistor maintains lower capacitance to prevent streaking in the pixel signal path.
3Measurement precision
If the current flowing through the differential transistor is increased to improve signal strength, then signal-to-noise ratio is improved, but the power consumption increases
Solution Approach 1:
The patent applies parameter changes by optimizing the gate width/gate length ratios of the differential transistors to achieve the desired current levels. By carefully selecting the W/L ratios, the patent achieves sufficient signal strength and signal-to-noise ratio while controlling the power consumption within acceptable limits. This allows the circuit to operate at optimal performance points without excessive power dissipation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces streaking, enhancing image quality by minimizing temporal fluctuations in the differential transistors and current, while maintaining low noise and power consumption, and allows for optimal image characteristics based on the type of image being captured.
Implementation Method 1
The comparator includes: a first differential transistor to which the reference signal is input; a second differential transistor to which the analog signals are input
Implementation Method 2
The counter is disposed so as to correspond to the comparator and obtains the digital signals by counting periods during which the comparator compares the analog signals with the reference signal
Implementation Method 3
A ratio between gate width/gate length of the first differential transistor and gate width/gate length of the second differential transistor is 1:N (N>1). In accordance with this configuration, a capacitance of a drain of the second differential transistor is increased without changing a size of the first differential transistor
Implementation Method 4
The first load transistor is connected between a drain terminal of the first differential transistor and a power supply. The second load transistor is connected between a drain terminal of the second differential transistor and the power supply. The current source transistor is connected between a ground and source terminals of the first differential transistor and the second differential transistor
Data Source
AI summary
A solid-state image pickup device includes: a pixel portion in which a plurality of pixels are arrayed in matrix; and an Analog-Digital converter. The Analog-Digital converter converts pixel signals, which are generated in the pixel portion, from analog signals into digital signals. The Analog-Digital converter includes: a comparator; and a counter. The comparator compares the analog signals, each of which corresponds to each of the plurality of pixels, with a reference signal. The comparator includes: a first differential transistor to which the reference signal is input; a second differential transistor to which the analog signals are input; a first load transistor; a second load transistor; and a current source transistor. A fluctuation of a voltage between a gate and a source of the first differential transistor is suppressed. This fluctuation follows a voltage fluctuation of a node connected commonly to the second differential transistor and the second load transistor.