Image Sensor Control Signal Sequencing Circuit
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Solution Overview
Problem
Current image sensors require complex sequencing circuits and numerous registers to generate control signals for various operating modes, making it difficult to easily switch between different modes and sequences, such as Global Shutter and Electronic Rolling Shutter modes, and to facilitate the programming of signals for pixels and readout circuits.
Innovation Solution
An image sensor with a programmable addressable memory and a sequencing circuit that generates control signals based on binary words, using a memory controller and control signal generation circuit to produce signals according to predetermined sequences, allowing for flexible programming and synchronization with the sensor's operation, including a synchronization control circuit to manage startup instants and series of control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate sequencing circuits and numerous registers are used for each control signal, then precise control signal sequencing is achieved, but device complexity increases significantly
Solution Approach 1:
The patent merges multiple separate sequencing circuits into a single unified sequencing circuit that generates all control signals (RESET, XSEL, YSEL, READ, SAMPLE, CONVERT) through one centralized state machine. This single circuit uses a unified register set to manage timing parameters for all signals, eliminating the need for separate sequencing logic for each signal and significantly reducing overall device complexity while maintaining precise sequencing control.
Solution Approach 2:
The unified sequencing circuit is designed to support multiple operating modes (Global Shutter and Electronic Rolling Shutter) through a single multi-functional architecture. The same sequencing circuit and register set can generate different control signal sequences by changing operational parameters, eliminating the need for mode-specific sequencing circuits and reducing device complexity across different operational scenarios.
2Manufacturing precision
If numerous registers are provided for programming each control signal, then precise timing control is achieved, but ease of operation decreases due to complex individual programming requirements
Solution Approach 1:
The patent combines multiple individual signal programming registers into a unified register structure where a single set of registers (RESET_TIME, XSEL_TIME, YSEL_TIME, READ_TIME, SAMPLE_TIME, CONVERT_TIME) controls the timing of all control signals. This unified approach allows timing parameters to be programmed in a coordinated manner rather than individually, significantly improving ease of operation while maintaining precise timing control for all signals.
3Adaptability or versatility
If mode-specific sequencing circuits are used for different operating modes, then adaptability to various modes is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal sequencing circuit that can operate in multiple modes (Global Shutter and Electronic Rolling Shutter) without requiring separate mode-specific circuits. The same unified sequencing logic adapts to different modes by utilizing the same register set with different timing parameter configurations, achieving high mode adaptability while minimizing device complexity through architectural reuse.
Data Source
AI summary
The invention relates to image sensors and more specifically the generation of control signals for pixels and readout circuits.The sequencing circuit which produces these signals comprises: a programmable memory (MEM) containing binary words (M0, M1, M2, etc.) in which each word comprises a group of several bits of position 1 to N, and in which the position i of a bit in a word corresponds to the position i of a respective control signal; a memory controller (CTRL_MEM) for extracting from the memory at a determined rate the words located at successive addresses of the memory from a start address to an end address; and a control signal generation circuit (GEN_TIMING) establishing each control signal of position i from the succession of bits of respective position i that are extracted from the memory by the controller, the control signal reproducing the successive values taken by the bit of position i at the clock rate.