Image Sensor A/D Counter Coding for Clock Skew Accuracy
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Solution Overview
Problem
In solid-state imaging apparatuses, significant skew in clock signals can lead to large errors in A/D conversion accuracy due to the simultaneous change in logical levels of multiple clock signals when incrementing counter codes.
Innovation Solution
The use of a counter code comprising low-order bit codes with phase-shifted clock signals and high-order bit codes based on gray codes, where the count value changes only the logical level of a 1-bit signal, limiting skew to minimize errors and ensuring accurate analog-to-digital conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple clock signals are used to increment counter code for high-resolution A/D conversion, then resolution is improved, but clock signal skew causes large errors in count value
Solution Approach 1:
The counter code is segmented into low-order bit code and high-order bit code. The low-order bit code uses multiple phase-shifted clock signals for fine resolution, while the high-order bit code uses a gray code counter that changes only one bit at a time for coarse resolution. This segmentation allows each part to serve its specific function without the skew problems affecting the entire system.
Solution Approach 2:
The counter code combines two different coding schemes: low-order bits use a multi-phase clock-based binary code for high resolution, while high-order bits use gray code for reliability. This composite approach merges the advantages of both coding methods to achieve both high resolution and immunity to clock skew errors.
2Measurement precision
If clock signal frequency is increased to improve resolution, then A/D conversion precision is improved, but clock signal skew and timing errors increase
Solution Approach 1:
The system uses periodic clock signals with specific phase relationships to increment the counter code. The low-order bit code uses multiple periodic clock signals with fixed phase shifts, while the high-order bit code uses periodic gray code sequences. This periodic structure ensures that timing relationships remain consistent and predictable, reducing timing errors.
Solution Approach 2:
The invention changes the coding parameter from standard binary to gray code for the high-order bits, and uses phase-shifted periodic clocks for low-order bits. This parameter change allows the system to achieve high resolution without requiring proportionally higher clock frequencies, thereby reducing timing errors and skew effects.
3Device complexity
If standard binary counter code is used for A/D conversion, then circuit simplicity is maintained, but clock skew causes large count value errors
Solution Approach 1:
The counter code is segmented into low-order bit code and high-order bit code. The low-order bit code uses multiple phase-shifted clock signals for fine resolution, while the high-order bit code uses a gray code counter that changes only one bit at a time for coarse resolution. This segmentation allows each part to serve its specific function without the skew problems affecting the entire system.
Solution Approach 2:
The counter code combines two different coding schemes: low-order bits use a multi-phase clock-based binary code for high resolution, while high-order bits use gray code for reliability. This composite approach merges the advantages of both coding methods to achieve both high resolution and immunity to clock skew errors.
Data Source
AI summary
There is a need to provide a solid-state imaging apparatus capable of highly accurately analog-to-digital converting an analog voltage output from a pixel circuit. The solid-state imaging apparatus supplies a counter code to an integral A/D converter. The counter code CD includes 3-phase clock signals and gray signals. The clock signals each have a cycle equal to specified cycle multiplied by 8 and allow phases to shift from each other by specified cycle. The gray signals linearly increase count values at a cycle equal to specified cycle multiplied by 4. The counter code reverses only the logical level of a signal when a count value changes. A count value error can be limited to a minimum.