Image Sensor Counter Circuit for Stable Noise-Resistant Sampling

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Solution Overview

Problem

Existing image sensors face challenges in accurately converting analog signals to digital signals due to coupling issues between signal lines, which can lead to noise and unreliable data, especially in high-definition imaging.

Innovation Solution

A counter circuit is introduced that performs complement and division operations using a D-latch and D-flip-flop configuration to stabilize count values, reducing the influence of coupling and enabling a reset multiple sampling technique for noise reduction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a counter circuit is used to convert analog signals to digital signals in high-definition image sensors, then the imaging resolution and detail are improved, but coupling issues between signal lines cause noise and reduce data reliability

Engineering Contradiction:
Improvesignal conversion accuracyVSAvoiddata reliability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent introduces a sampling unit as an intermediary component between the counter circuit and the output. This sampling unit captures and holds the count values at specific moments, preventing direct coupling between signal lines while maintaining accurate signal conversion. The sampling unit acts as a buffer that isolates the counter circuit from downstream noise and interference.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent performs complement operations on count values before they are fully processed or transmitted. By preliminarily adjusting the count values through complement operations, the system prepares the data in advance to be more resistant to noise and coupling issues, improving reliability before the signals undergo further processing.

Inventive Principle:
Principle #10Preliminary action

2Measurement precision

If signal lines are densely packed to achieve high-definition imaging, then the image quality and resolution are improved, but coupling between signal lines increases causing noise

Engineering Contradiction:
Improveimage resolutionVSAvoidsignal coupling noise
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The sampling unit serves as a spatial and temporal intermediary that separates densely packed signal lines. By capturing signals at discrete moments and holding them in storage elements, the sampling unit prevents direct electromagnetic coupling between adjacent signal lines while maintaining high-resolution imaging capability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent divides the continuous signal processing into discrete sampling intervals. By segmenting the signal flow into separate capture, hold, and process stages, the system reduces coupling noise between signal lines while preserving the high-definition image quality through precise temporal separation of signals.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentEP3962070B1Counter circuit and image sensor including the same
Publication Date: 2024.05.15 SAMSUNG ELECTRONICS CO LTD
  • EP3962070B1 patent drawingFigure 1
  • EP3962070B1 patent drawingFigure 2
  • EP3962070B1 patent drawingFigure 3

AI summary

An image sensor includes a pixel sensor configured to sense an incident light and to output an analog sampling signal; a sampling unit comparing the sampling signal and a ramp signal, and outputting a comparison signal having a duration that is indicative of the amplitude of the sampling signal; and a counter counting a length of the comparison signal based on a clock signal and first and second complement control signals. The counter includes an AND gate ANDing the comparison signal and the clock signal; and a counting unit triggered at a falling edge of the AND gate output to output a count value. The counting unit includes a complement operation controller storing an inverted count value that is an inversion of the count value in response to the first complement control signal, and outputting the inverted count value in response to the second complement control signal; and a D-flip-flop that is set or reset depending on the inverted count value, and outputs the count value.