Image Sensor Dark Current Reduction via Segmented Ion Implantation

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Solution Overview

Problem

Image sensors, particularly CMOS image sensors, suffer from excessive dark current due to impurities and substrate damage, leading to image degradation and poor performance.

Innovation Solution

A method involving ion implantation processes using boron as a doping impurity to minimize substrate damage and reduce dark current, including a first implantation process with high energy and dosage, a second implantation process with lower energy and dosage, and a third implantation process in the logic area using a two-part ion implantation process with boron and indium, along with the formation of shallow trench isolation features and transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional ion implantation processes are used to dope the substrate, then device performance is achieved, but substrate damage occurs and dark current increases

Engineering Contradiction:
Improvedevice performanceVSAvoidsubstrate damage and dark current
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The ion implantation process is divided into three separate implantation steps rather than one single process. Each implantation uses different parameters (energy, dosage, timing) to achieve cumulative doping while minimizing substrate damage at any single stage, thereby reducing dark current while maintaining device performance

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent varies key parameters of the ion implantation process including implantation energy (e.g., 100 keV, 200 keV, 400 keV), dosage (e.g., 1E12 to 1E14 atoms/cm²), and timing across three separate steps. These parameter changes allow optimization of doping effectiveness while controlling substrate damage and dark current generation

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If multiple ion implantation processes are performed to reduce dark current, then dark current is reduced, but processing complexity increases

Engineering Contradiction:
Improvedark currentVSAvoidprocessing complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent combines three separate ion implantation processes into a single integrated manufacturing flow, where each implantation step is sequentially performed on the same substrate without requiring separate processing lines or additional equipment. This merging approach reduces dark current while avoiding the complexity of multiple independent processing systems

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively reduces dark current in image sensors while maintaining current device performance, making it a cost-effective and efficient solution for improving image sensor performance.

Implementation Method 1

A method involving ion implantation processes using boron as a doping impurity to minimize substrate damage and reduce dark current

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS8368130B2Method and device to reduce dark current in image sensors
Publication Date: 2013.02.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US8368130B2 patent drawing
  • US8368130B2 patent drawing
  • US8368130B2 patent drawing

AI summary

A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel area and a logic area, forming a light sensing element in the pixel area, and forming a first transistor in the pixel area and a second transistor in the logic area. The step of forming the first transistor in the pixel area and the second transistor in the logic area includes performing a first implant process in the pixel area and the logic area, performing a second implant process in the pixel area and the logic area, and performing a third implant process only in the logic area.