Image Sensor Data Bus Parallel Precharge Evaluation
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Solution Overview
Problem
Conventional data bus control schemes for image sensors require additional circuitry and clock delay adjustments, leading to inefficiencies and increased cycle time in high-speed operations.
Innovation Solution
A method and apparatus that execute data bus precharging and sense amplifier evaluation in parallel, eliminating idle time and the need for additional circuits, and allowing the data bus to maintain a voltage after evaluation, thereby reducing cycle time and improving operational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If sequential operations (DBUS precharge, data loading, evaluation) are used in conventional systems, then each operation can be completed reliably, but the cycle time is prolonged and operational speed is reduced
Solution Approach 1:
The patent implements periodic action by dividing the operational cycle into distinct phases (precharge phase and evaluation phase) that alternate in a regular pattern. The DBUS is precharged during one phase, then isolated while evaluation occurs in the next phase, creating a periodic operational rhythm that enables parallel processing and reduces overall cycle time
Solution Approach 2:
The patent applies preliminary action by precharging the DBUS before the evaluation phase begins. The precharge operation is completed in advance during a dedicated precharge phase, so that when evaluation starts, the bus is already ready to receive and evaluate data, eliminating the need to wait for precharge completion during evaluation
2Ease of operation
If additional circuitry is added to generate control signals for sequential operations, then precise control of each operation phase is achieved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates unnecessary control circuitry by using the existing clock signal and its inverted version to directly control the precharge and evaluation phases. Instead of adding complex control signal generation circuits, the invention uses simple clock phases to trigger the appropriate operations, significantly reducing device complexity while maintaining precise control
Solution Approach 2:
The patent implements self-service by using the clock signal itself to automatically control the operational phases. The clock and its inverted version inherently provide the timing control needed for precharge and evaluation, eliminating the need for external control signal generation circuits and making the system self-regulating
3Reliability
If clock delay adjustment is implemented to accommodate frequency variations, then operational accuracy is maintained, but ease of operation is reduced and additional control circuits are needed
Solution Approach 1:
The patent applies universality by using the same clock signal for multiple functions: it controls both the precharge phase and the evaluation phase, and its inverted version controls the complementary operations. This multi-functional use of a single clock source eliminates the need for separate delay adjustment circuits for different frequency conditions
4Productivity
If the data bus is continuously active for both precharging and evaluation, then operational continuity is maintained, but power consumption increases
Solution Approach 1:
The patent implements periodic action by alternating between active precharge phases and active evaluation phases, with isolation periods in between. The DBUS is actively precharged only during designated precharge phases, then isolated during evaluation phases, creating a periodic pattern that maintains operational continuity while minimizing the time the bus is actively consuming power
Data Source
AI summary
A memory system including a plurality of memory cells configured to receive digital signals includes an address decoder, a data bus, and a sense amplifier configured to receive data output from memory cells activated by addresses from the address decoder. The pre-charging the data bus and evaluating previous data by the sense amplifier occurs substantially simultaneously during a first period. The data bus and the sense amplifier are isolated from each other during the first period.