Image Sensor Delay Calibration Circuitry for Gradient Mitigation
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Solution Overview
Problem
Large pixel arrays in image sensors face challenges due to significant RC time constants in row control lines, leading to delays during readout or integration, which can result in performance variations such as visible gradient effects or loss of full well charge.
Innovation Solution
The implementation of delay calibration circuitry, including a calibration row of dummy pixels and sampling circuits, to calibrate control line delays across the pixel array, thereby mitigating the effects of RC time constants.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the pixel array is made very large to increase imaging capability, then the area covered is improved, but the RC time constants in row control lines increase causing substantial delays
Solution Approach 1:
The patent divides the large pixel array into multiple smaller sub-arrays, each with its own row control lines. This segmentation reduces the length of individual control lines and their associated RC time constants, while still covering the same total imaging area through the collective coverage of multiple sub-arrays.
Solution Approach 2:
The patent introduces a column-direction readout mechanism that complements the row-direction control. By reading out pixels in the column direction through shared column control lines, the system effectively adds a dimensional approach to data retrieval, reducing the dependency on long row control lines for the entire array.
2Area of stationary object
If the pixel array is made very large to increase imaging capability, then the area covered is improved, but visible gradient effects appear across the horizontal dimension
Solution Approach 1:
By segmenting the large pixel array into smaller sub-arrays with independent row control, the patent eliminates the gradient effect that arises from long row control lines in monolithic arrays. Each sub-array can be controlled independently, ensuring uniform timing and signal levels across all regions.
Solution Approach 2:
The patent incorporates delay calibration circuitry that measures and compensates for timing variations in the readout process. This feedback mechanism adjusts the readout timing for different regions of the pixel array to compensate for any remaining RC time constant variations, eliminating visible gradient effects.
3Area of stationary object
If the pixel array is made very large to increase imaging capability, then the area covered is improved, but loss of full well charge occurs
Solution Approach 1:
The patent segments the large pixel array into smaller sub-arrays that can be read out more quickly due to shorter control line lengths. This reduces the time pixels remain in the integration capacitor, minimizing charge leakage and maintaining full well charge retention across the entire large array.
Solution Approach 2:
The patent implements delay calibration that performs preliminary timing adjustments before actual image capture. By pre-compensating for RC time constant variations and optimizing readout timing, the system ensures that charge is read out efficiently without excessive holding time that would cause leakage loss.
Data Source
AI summary
An image sensor may include an array of pixels and associated delay calibration circuitry for determining an amount of delay for row control signals. The delay calibration circuitry can include circuitry for generating a calibration row control signal, circuitry for propagating the calibration row control signal down a row of dummy pixels, and one or more sampling circuits coupled to one or more tap points in the row of dummy pixels for monitoring when the calibration row control signal arrives at the one or more tap points. The array of pixels can output signals during normal operation. The image sensor may include column readout circuitry for reading out the signals from the array of pixels. The column readout circuitry can be controlled using sampling signals that are progressively delayed based on count values output from the one or more sampling circuits.