Image Sensor Logic Circuit Noise Reduction via Dummy Data Segmentation

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Solution Overview

Problem

Existing image sensors face challenges in efficiently converting analog image signals to digital data without introducing noise, particularly due to overlapping periods of image data conversion and storage, which can result in image distortion and reduced quality.

Innovation Solution

The image sensor incorporates a logic circuit that converts image signals into data during one period and stores or outputs them during overlapping periods, with the option to write dummy data during non-overlapping periods to maintain a consistent ramp signal, thereby reducing noise and improving image quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If image data conversion and storage operations are performed in overlapping periods, then processing speed is improved, but noise is introduced and image quality deteriorates

Engineering Contradiction:
Improveprocessing speedVSAvoidnoise
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The patent segments the data output process into two distinct parts: real image data and dummy data. The logic circuit outputs real image data during the overlapping period when conversion is occurring, and outputs dummy data during non-overlapping periods. This segmentation allows the system to maintain high-speed processing while avoiding noise introduction, as the dummy data acts as a placeholder that prevents ramp signal changes from affecting image quality

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary action by pre-generating dummy data in advance and storing it in the logic circuit. This dummy data is prepared beforehand and ready to be output during non-overlapping periods. By having this preliminary preparation, the system can maintain consistent ramp signal levels without requiring complex real-time adjustments, thereby preventing noise while maintaining processing speed

Inventive Principle:
Principle #10Preliminary action

2Object-affected harmful factors

If dummy data is written during non-overlapping periods, then ramp signal consistency is maintained and noise is reduced, but device complexity increases

Engineering Contradiction:
ImprovenoiseVSAvoiddevice complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent uses dummy data as a simplified copy or placeholder representation during non-overlapping periods. Instead of performing complex operations or maintaining complex timing sequences, the system simply outputs pre-prepared dummy data that mimics the structure and format of real image data. This copying approach maintains ramp signal consistency and reduces noise while avoiding the need for complex control mechanisms

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent changes the parameter being output (from real image data to dummy data) based on the timing condition (overlapping vs. non-overlapping periods). This parameter change is controlled by a simple timing detection mechanism that identifies whether the current period is overlapping or non-overlapping. By changing this single parameter (data type) rather than implementing complex control logic, the system reduces noise while minimizing the increase in device complexity

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS11627270B2Image sensor
Publication Date: 2023.04.11 SAMSUNG ELECTRONICS CO LTD
  • US11627270B2 patent drawing
  • US11627270B2 patent drawing
  • US11627270B2 patent drawing

AI summary

An image sensor includes a pixel array; a logic circuit configured to convert an image signal generated from the pixel array during a first period into image data; and a memory. The image data may be written in the memory during a second period, of which at least a portion overlaps the first period. The logic circuit may write dummy data in the memory during a third period overlapping the first period and not overlapping the second period.