Image Sensor Dummy Lines Minimize Fixed Pattern Noise
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Solution Overview
Problem
Image sensors, particularly CMOS image sensors, face issues with column fixed-pattern noise (CFPN) due to differences in settling times between adjacent column lines caused by varying lengths of metal lines, leading to non-uniform signal transmission characteristics and noise in image output.
Innovation Solution
The image sensor design incorporates dummy column lines with the same overall length as effective column lines, ensuring all column lines have substantially equal capacitance and resistive-capacitive (RC) delay, thereby uniformizing signal transmission and minimizing CFPN.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If column lines have different lengths to accommodate pixel array layout, then pixel array coverage is improved, but signal transmission uniformity deteriorates causing CFPN
Solution Approach 1:
The patent applies local quality by adding dummy column lines specifically to columns with shorter effective lengths. This creates non-uniform local additions (dummy lines) to compensate for the underlying non-uniformity (different effective column lengths), making all total column line lengths substantially equal and thus uniformizing signal transmission characteristics across all columns.
Solution Approach 2:
The patent performs preliminary action by pre-calculating the length differences between column lines and determining the required dummy line lengths before fabrication. The dummy column lines are designed with specific lengths to compensate for effective length variations, ensuring that all column lines have substantially equal total lengths and uniform RC delay characteristics before the actual signal transmission occurs.
2Adaptability or versatility
If column lines have different lengths, then layout flexibility is improved, but settling time uniformity deteriorates
Solution Approach 1:
The patent applies local quality by adding dummy column lines specifically to columns with shorter effective lengths. This creates non-uniform local additions (dummy lines) to compensate for the underlying non-uniformity (different effective column lengths), making all total column line lengths substantially equal and thus uniformizing signal transmission characteristics across all columns.
Solution Approach 2:
The patent performs preliminary action by pre-calculating the length differences between column lines and determining the required dummy line lengths before fabrication. The dummy column lines are designed with specific lengths to compensate for effective length variations, ensuring that all column lines have substantially equal total lengths and uniform RC delay characteristics before the actual signal transmission occurs.
3Manufacturing precision
If dummy column lines are added to equalize lengths, then signal transmission uniformity is improved, but device complexity increases
Solution Approach 1:
The patent applies merging by combining the effective column lines (which carry actual pixel signals) with dummy column lines (which provide length compensation) into unified column line structures. The dummy lines are electrically connected to the effective lines through connection nodes, merging their functions into a single integrated interconnection system that achieves both signal transmission and length equalization.
Solution Approach 2:
The patent applies universality by designing the dummy column lines to serve multiple functions: they provide length compensation for RC delay equalization, maintain consistent signal transmission characteristics across all columns, and can be integrated into the existing interconnection layer structure without requiring separate compensation mechanisms for each column.
Data Source
AI summary
An image sensor and an electronic apparatus, the image sensor including a plurality of pixels, each pixel of the plurality of pixels including a photodiode and a transfer transistor, a reset transistor, a source-follower transistor, and a selection transistor, which correspond to the photodiode; a plurality of first interconnection lines connected to gates of the transfer transistor, the reset transistor, and the selection transistor, the plurality of first interconnection lines extending in a first direction; and a plurality of second interconnection lines connected to a source region of the selection transistor, the plurality of second interconnection lines extending in a second direction that intersects the first direction, wherein the plurality of second interconnection lines includes dummy lines on a peripheral area that is outside of a pixel area in which the pixels are located.