Image Sensor Ramp ADC Using Early Low-Bit Conversion
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Solution Overview
Problem
In laminated-type imaging apparatuses, miniaturizing pixels while maintaining image quality and speed is challenging due to the difficulty in downsizing analog-digital (AD) conversion circuits, which leads to time differences in reading signals from multiple pixels, potentially causing distorted images or longer image acquisition times, especially when imaging moving objects.
Innovation Solution
A conversion apparatus with a comparison unit that compares input signals with a ramp voltage to generate a digital signal of a predetermined bit number, utilizing a storage unit to hold code values repeatedly, allowing for the combination of low-order and high-order bits to create a digital signal, with the option for Gray codes and shared bits, and differing ramp signal cycles for high and low signal intensity levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple pixels share one AD conversion circuit, then the circuit size is reduced, but the reading time increases and image distortion occurs
Solution Approach 1:
The patent divides the AD conversion process into multiple segments by providing multiple AD conversion circuits (first AD conversion circuit and second AD conversion circuit). Each circuit handles a subset of pixels simultaneously, thereby reducing the total reading time while keeping each individual circuit compact in size.
Solution Approach 2:
The patent combines multiple AD conversion circuits to work in parallel for converting signals from multiple pixels. By merging the conversion capabilities of multiple circuits, the system achieves both size efficiency (compared to one giant circuit) and speed efficiency (through parallel processing).
2Area of moving object
If pixels are miniaturized, then the imaging apparatus size is reduced, but the AD conversion circuit becomes difficult to downsize
Solution Approach 1:
The patent segments the pixel array into multiple groups, each served by a dedicated AD conversion circuit. This segmentation allows each circuit to be simpler and smaller, making downsizing feasible while still supporting miniaturized pixels through parallel processing.
Solution Approach 2:
The patent transitions from a single sequential conversion approach to a multi-dimensional parallel conversion architecture. By adding the dimension of parallelism with multiple circuits operating simultaneously, the system accommodates miniaturized pixels without increasing individual circuit complexity.
3Device complexity
If one AD conversion circuit handles many pixels, then the circuit count is reduced, but time differences between read pixels increase
Solution Approach 1:
The patent segments the pixel-to-circuit mapping so that each AD conversion circuit handles a limited subset of pixels. This segmentation reduces the time differences in signal reading within each circuit while keeping the total number of circuits manageable through efficient resource allocation.
Solution Approach 2:
The patent implements dynamic signal routing where the switching circuit can flexibly assign different pixel groups to different AD conversion circuits based on timing requirements. This dynamic allocation optimizes timing accuracy by balancing the load across circuits to minimize reading time differences.
Data Source
AI summary
The present technology relates to a conversion apparatus, an imaging apparatus, an electronic apparatus, and a conversion method that are capable of reducing the scale of a circuit.The conversion apparatus includes: a comparison unit that compares an input voltage of an input signal and a ramp voltage of a ramp signal that varies with time; and a storage unit that holds a code value when a comparison result from the comparison unit is inverted, the holding of the code value by the storage unit being repeated a plurality of times, to generate a digital signal having a predetermined bit number. The predetermined bit number is divided into high-order bits and low-order bits, the low-order bits are acquired earlier than the high-order bits, and the acquired low-order bits and the high-order bits are combined with each other, to generate the digital signal having the predetermined bit number. The present technology can be applied to a portion of an image sensor, in which AD conversion is performed.