Image Sensor Fabrication via Simultaneous Capacitor and Contact Formation
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Solution Overview
Problem
Conventional methods for fabricating image sensors require additional processes and increased costs due to the need for separate formation of capacitor and contact structures, which can lead to unfilled trenches and the presence of metal silicide that necessitates extra photolithography and etching steps.
Innovation Solution
A method that simultaneously forms capacitor and contact structures by creating a conductive layer to fill and cover holes, followed by planarization using Chemical Mechanical Polishing (CMP), reducing the number of CMP processes and eliminating the need for additional photolithography and etching steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate processes are used to form capacitor and contact structures, then each structure can be formed with precise control, but the number of fabrication steps increases and costs increase
Solution Approach 1:
The patent combines the formation of capacitor electrodes and contact plugs into a single integrated process. The lower electrode of the capacitor and the contact plug are formed simultaneously through a unified deposition and planarization sequence, eliminating the need for separate fabrication steps while maintaining structural precision.
Solution Approach 2:
The lower electrode layer serves dual functions: it acts as both the capacitor electrode and the contact plug material. By using the same material layer for both purposes, the patent reduces the number of fabrication steps while ensuring consistent electrical properties for both capacitor and contact structures.
2Manufacturing precision
If additional planarizing processes are performed to fill trenches, then surface flatness is improved, but fabrication time and cost increase
Solution Approach 1:
The patent performs planarization during the capacitor formation process itself, before subsequent contact hole formation. The lower electrode is planarized to fill trenches and create a flat surface in advance, eliminating the need for additional planarizing steps later in the fabrication sequence.
Solution Approach 2:
The planarization step is merged with the capacitor electrode formation process. The same deposition and CMP sequence that creates the capacitor lower electrode also simultaneously fills and planarizes the surface, combining two functions into one integrated operation.
3Reliability
If metal silicide is used in gate and lower electrodes, then electrical conductivity is improved, but additional photolithography and etching steps are required to remove silicide in pixel regions
Solution Approach 1:
The patent applies different material compositions to different regions: metal silicide is used in the logic region for high conductivity, while the pixel array region uses alternative materials or structures that do not require silicide removal. This localized material selection eliminates unnecessary fabrication steps in sensitive regions.
Solution Approach 2:
The fabrication process is segmented by region: the logic region undergoes full metal silicide processing, while the pixel array region uses a modified process that avoids silicide formation or includes selective removal steps only where needed. This segmentation eliminates redundant processing steps across the entire device.
4Manufacturing precision
If multiple CMP processes are performed to form capacitor and contact structures, then structural precision is improved, but fabrication cost and complexity increase
Solution Approach 1:
The patent merges multiple CMP operations into a single integrated planarization step. The lower electrode is formed and planarized in one sequence, and this planarized surface is directly used for subsequent contact hole formation, eliminating the need for separate CMP processes between capacitor and contact structure fabrication.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces fabrication costs and increases the reliability of image sensors by simplifying the process and eliminating the need for extra CMP steps, while ensuring proper filling of trenches and removal of metal silicide.
Implementation Method 1
planarizing the second conductive layer to form a capacitor plug in the capacitor hole, a first contact plug in the first contact hole
Data Source
AI summary
A method of fabricating an image sensor which reduces fabricating costs through simultaneous formation of capacitor structures and contact structures may be provided. The method may include forming a lower electrode on a substrate, forming an interlayer insulating film on the substrate, the interlayer insulating film may have a capacitor hole to expose a first portion of the lower electrode. The method may further include forming a dielectric film on at least the first portion of the lower electrode, forming a first contact hole in the interlayer insulating film to expose a second portion of the lower electrode, forming a first conductive layer in at least the first contact hole and the capacitor hole, forming a second conductive layer on the first conductive layer to fill and cover the capacitor hole and the first contact hole, and planarizing the second conductive layer to simultaneously form a capacitor plug in the capacitor hole, a first contact plug in the first contact hole, an upper electrode beneath the capacitor plug, and a first contact barrier film beneath the first contact plug.