Image Sensor FIFO Buffer Allocation for Adaptive Pipeline Routing
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Solution Overview
Problem
Existing image processing systems fail to meet the requirements of image sensors due to inadequate allocation of buffers and memory channels, leading to compromised versatility and inefficiency in handling diverse image capturing scenarios.
Innovation Solution
An image receiving device and method that adaptively configures hardware resources by using a FIFO memory and multiplexer circuits to set pipeline parameters based on device information and data capacities, ensuring each image sensor is allocated to a suitable FIFO buffer and channel group.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If buffers and memory channels are allocated according to a fixed sequence, then the allocation process is simple and deterministic, but the system fails to meet diverse image capturing requirements of different image sensors
Solution Approach 1:
The patent implements dynamic allocation of buffers and memory channels to image sensors based on real-time detection of sensor types and capturing requirements. The system transitions from fixed sequential allocation to adaptive dynamic configuration, where the processor circuit determines optimal buffer-channel pairings based on image sensor characteristics and scene modes, thereby resolving the contradiction between adaptability and complexity.
Solution Approach 2:
The system changes allocation parameters (buffer data capacity, memory channel bandwidth) based on detected image sensor requirements. The processor circuit modifies allocation configurations dynamically according to sensor resolution, scene mode, and data throughput needs, enabling the system to adapt to diverse capturing requirements while managing complexity through parameter-based control.
2Reliability
If a buffer with insufficient data capacity is allocated to a high-resolution image sensor, then the buffer allocation is simple, but image data cannot be properly buffered
Solution Approach 1:
The system employs feedback mechanisms where the processor circuit detects image sensor characteristics and buffering requirements, then adjusts buffer allocations accordingly. The FIFO multiplexer circuit receives feedback about data capacity needs and dynamically configures buffer assignments to match sensor requirements, ensuring reliable image data buffering while maintaining allocation efficiency through intelligent feedback-driven decisions.
Solution Approach 2:
The system performs preliminary detection of image sensor types and requirements before allocating buffers and memory channels. The processor circuit pre-configures appropriate buffer data capacities and channel bandwidths based on anticipated sensor needs, preventing allocation mismatches before they occur and ensuring reliable buffering from the outset.
3Adaptability or versatility
If a memory channel that does not support special scene modes is allocated to an image sensor, then the channel allocation is straightforward, but the sensor cannot perform special scene mode capturing
Solution Approach 1:
The patent implements a universal memory channel allocation system where the processor circuit identifies scene mode requirements and assigns channels with appropriate capabilities. The FIFO multiplexer circuit provides multi-functional channel assignment, enabling the same hardware infrastructure to support multiple scene modes by dynamically routing sensors to channels with matching capabilities, thereby achieving versatility without proportionally increasing physical device complexity.
Data Source
AI summary
An image receiving device includes a first-in-first-out (FIFO) memory, a processor circuit and a FIFO multiplexer circuit. The FIFO memory includes a plurality of FIFO buffers. The processor circuit sets a plurality of first pipeline parameters according to device information of a plurality of image sensors and data capacities of the FIFO buffers. The FIFO multiplexer circuit configures correspondence between the image sensors and the FIFO buffers according to the first pipeline parameters, such that each of the image sensors transmits image data to a corresponding one of the FIFO buffers.