Image Sensor Pixel Readout Layout for Higher Fill Factor

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Solution Overview

Problem

Conventional image sensors require multiple bias and reset signal lines, which decrease the fill factor and lead to poor Gb/Gr balance due to the need for metal wires to span across the pixel array during manufacturing.

Innovation Solution

The image sensor integrates the reset voltage and bias voltage signal lines into the same circuit node and signal line of the column readout circuit, reducing the need for additional metal wires and improving fill factor and Gb/Gr balance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple bias signal lines and reset signal lines are provided to respectively provide bias voltages and reset voltages, then the reset function and bias function are achieved, but the fill factor decreases and Gb/Gr balance deteriorates

Engineering Contradiction:
Improvereset functionVSAvoidfill factor
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent merges the reset signal line and bias signal line into a single shared signal line that carries both reset voltage and bias voltage. The column readout circuit is configured to receive both signals through this shared line, eliminating the need for separate metal wires for reset voltage distribution across the pixel array. This consolidation directly improves the fill factor by removing redundant metal wire structures while maintaining both reset and bias functions.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shared signal line between the pixel circuit and column readout circuit serves multiple functions: it acts as both a reset voltage transmission line and a bias voltage transmission line. The column readout circuit is designed to selectively process different signals (reset signal and bias signal) through the same physical pathway, making the signal line universal and multi-functional. This reduces the overall number of signal lines required in the system.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If multiple metal wires are provided for bias and reset signals, then the reset and bias functions are achieved, but the Gb/Gr balance deteriorates

Engineering Contradiction:
Improvebias functionVSAvoidGb/Gr balance
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent combines the bias signal line and reset signal line into a single shared signal line, so that both green blue (Gb) and green red (Gr) pixel circuits receive their bias and reset signals through the same physical pathway. This merging ensures that any variations in signal transmission affect both color channels equally, thereby maintaining good Gb/Gr balance and improving manufacturing precision for color uniformity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent applies different signal processing configurations to different regions of the pixel array. Specifically, pixel circuits of different color types (Gb and Gr) are configured to receive signals through the shared line with optimized local connections, ensuring that each color channel receives appropriate bias and reset signals while maintaining overall balance. This local optimization within the unified signal distribution framework improves Gb/Gr balance.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS12279062B2Image sensor and operation method thereof
Publication Date: 2025.04.15 GUANGZHOU TYRAFOS SEMICON TECH CO LTD
  • US12279062B2 patent drawing
  • US12279062B2 patent drawing
  • US12279062B2 patent drawing

AI summary

An image sensor and an operation method thereof are provided. The image sensor includes a pixel circuit and a column readout circuit. The pixel circuit includes a pixel unit, a transfer transistor, a reset transistor, a readout transistor and a selection transistor. The column readout circuit includes a first circuit node and a second circuit node. A first terminal of the first reset transistor and a first terminal of the first readout transistor are coupled to a first circuit node, and a second terminal of the first select transistor is coupled to a second circuit node.