Solid State Image Sensor Fine Plug Interconnect
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Solution Overview
Problem
Existing techniques for laminating semiconductor substrates to form solid state image sensors face challenges in achieving efficient electrical connections between multiple substrates, particularly due to the large diameter of silicon through-electrodes (TSV) which hinder pixel array integration and result in long current paths, increased power consumption, and noise variations.
Innovation Solution
The solution involves a solid state image sensor design where a first semiconductor substrate with an insulating film on its rear surface and a second substrate with an interlayer insulating film on its surface are joined, using conductive connection parts that penetrate the insulating film and are embedded in connection holes, allowing for finer electrical connections without the need for large silicon through-electrodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon through-electrodes (TSV) are used to electrically connect laminated semiconductor wafers, then electrical connection between substrates is achieved, but the large diameter of TSV makes it difficult to place in pixel arrays and results in long current paths
Solution Approach 1:
The patent divides the electrical connection path into multiple segments: connection holes through the first substrate, intermediate conductive layers, and connection holes through the second substrate. This segmentation allows each component to be optimized independently, reducing the overall current path length while maintaining reliable electrical connection between laminated substrates
Solution Approach 2:
The patent transitions from vertical through-substrate connections (TSV) to a combination of vertical connection holes and lateral conductive paths within interlayer insulating films. This dimensional change allows current to travel shorter distances by utilizing the intermediate layer space, reducing current path length while achieving reliable electrical connection
2Reliability
If silicon through-electrodes (TSV) are used to connect laminated substrates, then electrical connection is established, but power consumption increases due to long current paths
Solution Approach 1:
The patent segments the electrical connection into multiple short paths through connection holes and intermediate conductive layers, replacing the single long TSV path. This segmentation reduces the total resistance and current path length, thereby reducing power consumption while maintaining reliable electrical connection between substrates
Solution Approach 2:
The patent changes the geometric parameters of the connection structure by using multiple smaller connection holes with optimized dimensions and spacing, rather than a single large TSV. This parameter optimization reduces the overall resistance and inductance of the connection path, reducing power consumption while ensuring reliable electrical connection
3Reliability
If silicon through-electrodes (TSV) are used for substrate connection, then electrical connection is achieved, but noise variations increase
Solution Approach 1:
The patent divides the single long TSV connection into multiple shorter connection segments through connection holes and intermediate conductive layers. This segmentation reduces the inductance and resistance of each segment, minimizing signal integrity issues and noise variations while maintaining reliable electrical connection between substrates
Solution Approach 2:
The patent introduces intermediate conductive layers and interlayer insulating films as mediators between the laminated substrates. These intermediate structures provide controlled impedance paths and shielding, reducing electromagnetic interference and noise variations while ensuring stable electrical connection
4Strength
If main surface sides of semiconductor wafers are joined to each other, then bonding is achieved, but three semiconductor wafers or more cannot be laminated
Solution Approach 1:
The patent segments the bonding interface by forming insulating films on specific surfaces (rear surface of first substrate, main surface of second substrate) rather than requiring complete surface coverage. This segmentation allows multiple wafers to be laminated by creating independent bonding interfaces at different locations, enabling three or more wafers to be stacked while maintaining strong bonding at each interface
Solution Approach 2:
The patent utilizes different surfaces (rear surface and main surface) of substrates for bonding, transitioning from a single-surface bonding approach to a multi-surface approach. This dimensional utilization allows multiple wafers to be laminated in sequence, increasing the number of laminated wafers while maintaining strong bonding strength at each interface
Data Source
AI summary
In a solid state image sensor having two semiconductor substrates or more laminated longitudinally, electrical connection between the semiconductor substrates is made by a fine plug. An insulating film covering a first rear surface of a semiconductor substrate having a light receiving element, and an interlayer insulating film covering a second main surface of a semiconductor substrate mounting a semiconductor element are joined to each other. In its joint surface, a plug penetrating the insulating film and a lug embedded in a connection hole in an upper surface of the interlayer insulating film are joined, and the light receiving element and the semiconductor element are electrically connected through the plugs.