Image Sensor Gate Dielectric Layout for Deep Trench Pixel Scaling
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Solution Overview
Problem
Conventional CMOS image sensors face challenges in scaling down dimensions due to issues with shallow trench isolation and contact etch stop layer processes, which affect dark current, full well capacity, and white pixel performance, and limit the ability to develop extremely small pixel pitch sensors.
Innovation Solution
The implementation of a deep trench isolation structure with a first gate dielectric structure of a specific thickness and a second gate dielectric structure of greater thickness, which serves as a safe landing area for the trench formation process, allowing for a larger gate electrode and conductive contact placement closer to the trench, enhancing charge transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional shallow trench isolation and contact etch stop layer processes are used, then manufacturing is simpler, but device scaling is limited and performance deteriorates
Solution Approach 1:
The gate dielectric layer is segmented into two distinct structures with different thicknesses: a first gate dielectric structure with a first thickness and a second gate dielectric structure with a second thickness greater than the first thickness. This segmentation allows the thinner region to enable device scaling while the thicker region provides process margin during trench formation, resolving the contradiction between scaling capability and manufacturing precision.
Solution Approach 2:
Different regions of the gate dielectric are given different local qualities through varying thicknesses. The first gate dielectric structure has a thinner thickness optimized for device operation and scaling, while the second gate dielectric structure has a thicker thickness optimized for process robustness during trench formation. This local differentiation resolves the contradiction by allowing each region to serve its specific function optimally.
2Productivity
If gate electrode and conductive contact are placed closer to the trench, then charge transfer efficiency improves, but risk of damage during trench formation increases
Solution Approach 1:
The second gate dielectric structure with greater thickness is formed beforehand in regions adjacent to the trench, creating a cushioning effect. This thicker dielectric structure provides a safety margin that protects the gate electrode and conductive contact from damage during trench formation processes, while still allowing them to be positioned close to the trench for optimal charge transfer efficiency.
Solution Approach 2:
The second gate dielectric structure acts as an intermediary element between the trench isolation and the gate electrode/conductive contact. It provides a protective buffer zone that mediates the interaction between the aggressive trench formation process and the sensitive electronic structures, enabling close placement without compromising reliability.
3Length of moving object
If image sensor dimensions are scaled down, then device size reduces, but manufacturing precision and yield deteriorate
Solution Approach 1:
The solution addresses the two-dimensional scaling problem by introducing a vertical dimension variation in the gate dielectric thickness. While the pixel pitch is reduced in the horizontal plane, the gate dielectric thickness is varied in the vertical dimension, providing an additional degree of freedom to maintain manufacturing precision during trench formation even as lateral dimensions are scaled down.
Data Source
AI summary
Various embodiments of the present disclosure are directed towards an image sensor. The image sensor includes a deep trench isolation (DTI) structure disposed in a substrate. A pixel region of the substrate is disposed within an inner perimeter of the DTI structure. A photodetector is disposed in the pixel region of the substrate. A gate electrode structure overlies, at least partially, the pixel region of the substrate. A first gate dielectric structure partially overlies the pixel region of the substrate. A second gate dielectric structure partially overlies the pixel region of the substrate. The gate electrode structure overlies both a portion of the first gate dielectric structure and a portion of the second gate dielectric structure. The first gate dielectric structure has a first thickness. The second gate dielectric structure has a second thickness that is greater than the first thickness.


