Image Sensor Gate Dielectric Thickness Optimization
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Solution Overview
Problem
Image sensors face issues with blinking pixels, time-variant noise, and high power consumption due to variations in transistor gate dielectric layer thicknesses.
Innovation Solution
The image sensor design includes a pixel array with transistors having gate dielectric layers of varying thicknesses, specifically thinner layers for the drive transistor to reduce random telegraph signal noise and power consumption, while maintaining efficient charge transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform thickness gate dielectric layers are used in all transistors, then manufacturing process is simple, but blinking pixels and time-variant noise increase
Solution Approach 1:
The patent applies different gate dielectric layer thicknesses to different transistor types within the pixel unit. Specifically, the drive transistor has a thinner gate dielectric layer (first thickness) while other transistors have thicker gate dielectric layers (second thickness). This local differentiation reduces random telegraph signal noise and blinking pixels in the drive transistor without unnecessarily complicating other transistors.
Solution Approach 2:
The gate dielectric layer structure is segmented into at least two different thickness regions corresponding to different transistor functions. The drive transistor region receives a thinner gate dielectric layer while other transistor regions receive thicker gate dielectric layers, allowing optimized performance for each functional segment.
2Use of energy by moving object
If thicker gate dielectric layers are used in all transistors, then manufacturing precision is easier to maintain, but power consumption increases
Solution Approach 1:
The patent optimizes power consumption by applying thinner gate dielectric layers specifically to the drive transistor where low noise is critical, while maintaining thicker gate dielectric layers in other transistors where noise is less problematic. This localized optimization reduces overall power consumption without requiring ultra-precise control across all transistor types.
3Reliability
If thinner gate dielectric layers are used in drive transistor, then random telegraph signal noise is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the gate dielectric layer fabrication into at least two process stages: first forming a thicker gate dielectric layer across all transistor regions, then selectively thinning the gate dielectric layer in the drive transistor region. This segmented approach reduces random telegraph signal noise in the drive transistor while maintaining manageable manufacturing complexity through a systematic two-step process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively minimizes blinking pixels and time-variant noise while reducing power consumption by optimizing the thickness of gate dielectric layers in the transistors, enhancing the overall performance and efficiency of the image sensor.
Implementation Method 1
each of the pixel units includes a photodiode and a plurality of transistors on or over a semiconductor substrate
Data Source
AI summary
An image sensor is disclosed. The image sensor includes a pixel array including a plurality of pixel units, a controller configured to drive the pixel array, and an analog-digital conversion block configured to convert a sensing signal output from the pixel array to a digital signal, wherein each of the pixel units includes a photodiode and a plurality of transistors on a semiconductor substrate, each of the transistors includes a gate electrode and a gate dielectric layer, each gate dielectric having a thickness, and the thickness of at least one of the gate dielectric layers is different from the thickness of at least one of the other gate dielectric layers.


