Image Sensor Readout With Shared Gray Code for Faster Low-Power ADC
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional image sensors face challenges with high power consumption and non-uniform power draw due to large instantaneous current surges during analog-to-digital conversion, especially in high frame rate and large pixel count applications, which limits ADC clocking speed and overall performance.
Innovation Solution
The implementation of a shared Gray code generator and parallel column arithmetic logic units for parallel analog-to-digital conversion, allowing for correlated double sampling and efficient conversion of analog image signals from column bit lines, reducing power consumption and improving ADC speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional column based ripple counter is used for ADC, then the analog image signal can be converted to digital image signal, but the power consumption increases significantly due to large instantaneous current surge during ADC period
Solution Approach 1:
The patent divides the ADC operation into multiple phases using separate counters: a first counter handles the ramp signal counting while a second counter handles the digital output generation. This segmentation allows the counting operation to be spread over time rather than concentrated in a single ripple counter, reducing instantaneous current demand while maintaining conversion accuracy.
2Measurement precision
If the clock frequency of the counter is increased to achieve higher resolution digital image signal output, then the time resolution is improved, but the power consumption of the counter increases
Solution Approach 1:
The patent implements dynamic clocking where the counter operates at high frequency only during the brief ADC conversion period and then transitions to a lower frequency or idle state. The counter is enabled only when needed for conversion, allowing high time resolution during conversion while minimizing average power consumption through dynamic frequency adjustment.
3Power
If a conventional ripple counter is used, then the ADC operation can be performed, but large voltage (IR) drops occur due to large current surge, limiting the maximum ADC clocking speed
Solution Approach 1:
The patent introduces an intermediary current mirror circuit that decouples the high-speed counting operation from the physical current draw. The current mirror allows the counter to operate at high frequencies by providing virtual current paths, reducing actual current surges through the supply network and minimizing voltage drops while maintaining high ADC clocking speed.
Data Source
AI summary
A readout circuit for use in an image sensor includes a plurality of comparators. Each one of the plurality of comparators is coupled to receive a ramp signal and a respective analog image data signal from a respective one of a plurality of column bit lines to generate a respective comparator output. Each one of a plurality of arithmetic logic units (ALUs) is coupled to receive phase-aligned Gray code (GC) outputs generated by a GC generator. Each one of the plurality of ALUs is further coupled to a respective one of the plurality of comparators to receive the respective comparator output. Each one of the plurality of ALUs is coupled to latch the phase-aligned GC outputs in response to the respective comparator output to generate a respective digital image data signal.