Image Sensor Ramp Circuit for Stable HDR Ground Voltage

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Solution Overview

Problem

Existing image sensors face challenges in maintaining a stable ground voltage during high dynamic range (HDR) image capture due to changes in the operation region of the ramp signal generated by the ramp voltage generating circuit, which affects the discharge operation of the input capacitor in the correlated double sampling (CDS) circuit.

Innovation Solution

The image sensor incorporates a ramp signal generating circuit that outputs reference ramp signals with varying slopes in different periods, an offset voltage sampling circuit to maintain a consistent DC level, and a buffer to stabilize the ramp signal, along with an analog-to-digital conversion (ADC) circuit for pixel signal conversion, thereby preventing significant changes in the operating region of the ramp signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the ramp signal generating circuit changes the operation region of the ramp signal to implement HDR image capture, then the dynamic range is extended, but the ground voltage changes due to discharge operation of the input capacitor

Engineering Contradiction:
Improvedynamic rangeVSAvoidground voltage
Core Design Contradiction:
Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The patent applies preliminary action by pre-charging the input capacitor to a specific voltage level before the discharge operation. This preliminary charging ensures that when the capacitor discharges during the ramp signal operation, the ground voltage remains stable because the capacitor is already prepared with the appropriate charge level, preventing voltage fluctuations during HDR capture modes.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent utilizes parameter changes by adjusting the voltage level of the input capacitor based on the operating mode. Different voltage levels are applied to the input capacitor depending on whether the sensor is operating in full-frame or sub-frame mode, allowing the system to adapt to different dynamic range requirements while maintaining stable ground voltage through controlled parameter adjustment.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If the analog gain changes to implement HDR image capture, then the dynamic range is extended, but the operating region of the ramp signal changes causing pedestal errors

Engineering Contradiction:
Improvedynamic rangeVSAvoidpedestal error
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent applies parameter changes by adjusting the voltage level of the input capacitor according to the operating mode. When switching between full-frame and sub-frame modes, the capacitor voltage is changed to appropriate levels, which compensates for the operating region changes of the ramp signal and eliminates pedestal errors while maintaining measurement precision.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system implements feedback by monitoring the operating mode and automatically adjusting the input capacitor voltage accordingly. This feedback mechanism ensures that the capacitor is always at the correct voltage level for the current operating mode, preventing pedestal errors that would otherwise occur due to mismatched voltage levels during HDR transitions.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12513435B2Image sensor and electronic device including the same
Publication Date: 2025.12.30 SAMSUNG ELECTRONICS CO LTD
  • US12513435B2 patent drawing
  • US12513435B2 patent drawing
  • US12513435B2 patent drawing

AI summary

An image sensor includes a pixel array, a ramp signal generating circuit configured to output a first reference ramp signal of a first slope as a first ramp signal in a first period and a second reference ramp signal of a second slope as the first ramp signal in a second period, an offset voltage sampling circuit configured to, to sample an offset voltage based on a DC level of the first reference ramp signal, to output the first ramp signal in the first period, and to output a signal obtained by adding the offset voltage to the first ramp signal as a second ramp signal in the second period, a buffer configured to buffer the first ramp signal and the second ramp signal, and an ADC circuit configured to compare a pixel signal from the pixel array with the first ramp signal or the second ramp signal.