Solid-State Image Sensor Insulating Film Planarization
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Solution Overview
Problem
Existing solid-state image sensors face sensitivity differences between the center and periphery due to uneven coverage of insulating films, leading to shading issues caused by global steps in the interlayer insulating film surface.
Innovation Solution
A solid-state image sensor design that includes a first insulating film covering photoelectric converters and transfer gate electrodes, a second insulating film on MOS transistor gate electrodes in the peripheral circuit area, and an interlayer insulating film contacting both, which are planarized using CMP to reduce coverage differences and flatten the surface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single insulating film is formed to cover both photodiodes and peripheral circuit areas simultaneously, then manufacturing process is simplified, but global steps remain causing sensitivity differences and shading
Solution Approach 1:
The insulating film formation process is divided into two separate steps: first forming an insulating film (3a) covering the pixel area, then forming a second insulating film (3b) covering the peripheral circuit area. This segmentation allows each area to receive appropriate insulation coverage, eliminating global steps while maintaining manufacturing feasibility through sequential processing.
Solution Approach 2:
Different insulating film structures are applied to different areas: the pixel area receives insulating film (3a) covering photodiodes and transfer gate electrodes, while the peripheral circuit area receives insulating film (3b) covering MOS transistor gate electrodes. This local differentiation ensures optimal surface flatness and sensitivity uniformity across the entire chip by addressing the specific requirements of each region.
2Manufacturing precision
If insulating film coverage is increased in peripheral circuit area to match pixel area, then surface flatness improves, but device complexity increases
Solution Approach 1:
The solution segments the insulating film structure into two distinct films: insulating film (3a) for the pixel area and insulating film (3b) for the peripheral circuit area. This segmentation achieves uniform surface flatness across both regions while maintaining clear functional differentiation, avoiding the need for a single complex multi-layer structure that would cover the entire chip uniformly.
Solution Approach 2:
The insulating films are formed in a predetermined sequence: first insulating film (3a) is formed covering the pixel area, then second insulating film (3b) is formed covering the peripheral circuit area. This preliminary action approach ensures that each area receives appropriate insulation coverage in the optimal processing sequence, achieving surface flatness without requiring post-formation complex adjustments or additional structural elements.
3Ease of manufacture
If insulating film is not formed on peripheral circuit gate electrodes, then manufacturing is simplified, but sensitivity differences cause shading
Solution Approach 1:
The patent applies local quality by forming insulating film (3b) specifically on MOS transistor gate electrodes in the peripheral circuit area, while maintaining the distinct structure of insulating film (3a) in the pixel area. This localized insulation coverage ensures uniform sensitivity across the entire chip by preventing the shading effect, while the segmented approach keeps the manufacturing process manageable through area-specific processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces sensitivity differences and improves surface flatness, minimizing shading by ensuring uniform coverage and planarization across the pixel and peripheral circuit areas.
Implementation Method 1
A planarization technique called CMP (Chemical Mechanical Polishing) is used to planarize the surface of an interlayer insulating film in a solid-state image sensor.
Data Source
AI summary
A solid-state image sensor having a pixel array area where a plurality of pixels are arranged, and a peripheral circuit area, each pixel including a photoelectric converter, and a transfer gate electrode which forms a channel for transferring charges generated by the photoelectric converter to a floating diffusion portion, comprises a first insulating film arranged to cover an upper surface of the photoelectric converter, at least part of an upper surface of the transfer gate electrode, and a side surface of the transfer gate electrode, a second insulating film arranged on a gate electrode of a MOS transistor arranged in the peripheral circuit area, and an interlayer insulating film arranged in contact with the first insulating film and the second insulating film.