CMOS Image Sensor Isolation Depth Tuning for Dark Current
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Solution Overview
Problem
Existing shallow-trench isolation (STI) structures in CMOS image sensors face challenges with dark current and crosstalk due to trench depth limitations during etching, where reducing trench depth to minimize dark current increases crosstalk, and vice versa.
Innovation Solution
The method involves forming doped regions in the substrate with controlled depth and performing selective etching to create trenches with vertical sidewalls, allowing for precise tuning of STI structure depth to balance dark current and crosstalk, using ion implantation and chemical etching processes to form isolation features with varying depths for different pixel and logic device regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If uniform isolation depth is used across all regions, then manufacturing is simplified, but performance optimization for different device regions is limited
Solution Approach 1:
The patent applies local quality by forming first isolation features with a first depth in a first region and second isolation features with a second depth in a second region. This allows each device region to have customized isolation depth optimized for its specific performance requirements, whether that prioritizes dark current suppression or crosstalk prevention, while still using standardized fabrication processes.
Solution Approach 2:
The isolation structure is segmented into multiple depth levels that can be independently controlled. By dividing the isolation system into first and second isolation features at different depths, the patent enables region-specific performance optimization without requiring completely different fabrication approaches for each region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces dark current and crosstalk by enabling precise control over the depth of isolation features, improving the performance of CMOS image sensors by minimizing current leakage and inter-device interference.
Implementation Method 1
performing a selective etching process to remove the doped region with respect to the substrate based on etch selectivity between the doped region and the substrate
Implementation Method 2
forming doped regions in the substrate with controlled depth and performing selective etching to create trenches with vertical sidewalls, allowing for precise tuning of STI structure depth to balance dark current and crosstalk, using ion implantation and chemical etching processes
Implementation Method 3
using ion implantation and chemical etching processes to form isolation features with varying depths for different pixel and logic device regions
Data Source
AI summary
A semiconductor device includes a substrate having a first device and a second device, where at least one of the first device and the second device includes a photo-sensitive element. The semiconductor device includes a first isolation feature surrounding the first device, where the first isolation feature has a first depth. The semiconductor device includes a second isolation feature surrounding the second device, where the second isolation feature has a second depth and where the first depth is greater than the second depth.