CMOS Image Sensor Charge-Holding Junction Layout for Dark Current Noise
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Solution Overview
Problem
CMOS image sensors experience increased dark current noise due to varying time periods for charge holding, leading to noise differences across images and potential shading, especially with whole-pixel simultaneous electronic shutters, and there is a desire to reduce noise even without this feature.
Innovation Solution
A solid-state imaging device with a photoelectric conversion portion and charge holding portion designed to reduce dark current noise, featuring a p-n junction positioned deeper in the charge holding portion and higher impurity concentration in the charge holding region compared to the photoelectric conversion region, allowing for simultaneous electronic shutter operation while minimizing noise variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the area of charge holding portion is widened or impurity concentration is increased to ensure sufficient saturation electric charges, then the charge holding capacity is improved, but dark current noise increases and image quality lowers
Solution Approach 1:
The patent applies local quality by creating different impurity concentration zones within the charge holding portion. Specifically, the third semiconductor region has a first impurity concentration while the fourth semiconductor region has a second impurity concentration that is lower than the first. This spatial variation in impurity concentration allows the charge holding portion to maintain sufficient charge storage capacity in regions with higher impurity concentration while reducing dark current noise in regions with lower impurity concentration, thereby resolving the contradiction between charge holding capacity and noise reduction.
2Ease of operation
If the whole-pixel simultaneous electronic shutter operates, then the exposure control is improved, but noise differences across image positions occur due to varying charge holding time periods
Solution Approach 1:
The patent applies parameter changes by systematically varying the impurity concentration parameter within the charge holding portion. The third semiconductor region is doped with a first impurity concentration and the fourth semiconductor region is doped with a second impurity concentration lower than the first. This parameter variation creates a gradient structure that compensates for the effects of different charge holding times across pixels, reducing position-dependent noise differences while maintaining the benefits of whole-pixel simultaneous electronic shutter operation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces dark current noise across the image, enhancing image quality and performance by ensuring consistent noise levels across pixels, even during whole-pixel simultaneous electronic shutter operations.
Implementation Method 1
a photoelectric conversion portion which photoelectrically converts incident light to generate a signal charge
Data Source
AI summary
A solid-state imaging device including a plurality of pixels including a photoelectric conversion portion, a charge holding portion accumulating a signal charge transferred from the photoelectric conversion portion, and a floating diffusion region to which the signal charge of the charge holding portion is transferred, wherein the photoelectric conversion portion includes a first semiconductor region of a first conductivity type, and a second semiconductor region of a second conductivity type formed under the first semiconductor region, the charge holding portion includes a third semiconductor region of the first conductivity type, and a fourth semiconductor region of the second conductivity type formed under the third semiconductor region, and a p-n junction between the third semiconductor region and the fourth semiconductor region is positioned deeper than a p-n junction between the first semiconductor region and the second semiconductor region.