Stack-Type Image Sensor Junction Regions for Plasma Etching Noise
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Solution Overview
Problem
Image sensors face degradation due to fine noise generated by plasma etching, which affects the performance of analog circuits, particularly in stack-type image sensors where electric charges from plasma etching can damage transistors.
Innovation Solution
The implementation of junction regions in both the upper and lower semiconductor layers to absorb and redirect electric charges generated during plasma etching, thereby protecting the transistors and reducing noise-induced degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If plasma etching is used to form contact wiring and wiring layers, then manufacturing precision and device functionality are improved, but electric charges generated during plasma etching cause fine noise that degrades analog circuit performance
Solution Approach 1:
A dedicated noise reception wiring is introduced as an intermediary element between the plasma etching process and the analog circuits. This wiring acts as a mediator that captures and isolates the electric charges generated during plasma etching, preventing them from directly affecting the analog circuit nodes and thus reducing fine noise while maintaining manufacturing precision
Solution Approach 2:
The harmful electric charges generated during plasma etching are extracted and redirected to a separate noise reception wiring. By removing these charges from the normal signal paths and concentrating them in a dedicated reception wiring, the fine noise affecting analog circuits is eliminated while the contact wiring formation precision is preserved
2Productivity
If stack-type image sensor structure is implemented, then integration density and productivity are improved, but electric charges from plasma etching can damage transistors in both upper and lower semiconductor layers
Solution Approach 1:
The image sensor is divided into upper and lower semiconductor layers with separate noise reception wirings for each layer. This segmentation allows independent management of electric charges in each layer, enabling the stack-type structure to maintain high integration density while providing targeted protection against plasma etching charges in both upper and lower transistors
Solution Approach 2:
Separate noise reception wirings are introduced as intermediary elements in both the upper and lower semiconductor layers. These wirings act as protective mediators that capture electric charges generated during plasma etching in各自的 layers, preventing charge damage to transistors while maintaining the high integration density of the stack structure
3Reliability
If junction regions are added to absorb electric charges, then reliability of analog circuits is improved, but device complexity increases
Solution Approach 1:
The noise reception wirings serve multiple functions: they act as charge collection paths during plasma etching, provide electrostatic discharge paths for protecting analog circuits, and can be integrated into existing wiring layers without requiring completely separate structures. This multi-functionality improves reliability while minimizing the increase in device complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces or prevents the degradation of analog circuits by effectively managing and redirecting electric charges, enhancing the performance and reliability of stack-type image sensors.
Implementation Method 1
electric charges generated by plasma etching
Implementation Method 2
removing electric charges generated by plasma etching using a junction region
Data Source
AI summary
An image sensor includes a first semiconductor layer having a first semiconductor region and a first insulating region, and a second semiconductor layer under the first semiconductor layer including a second semiconductor region and a second insulating region. The first semiconductor layer includes a first transistor having first source or drain regions in the first semiconductor region and a first gate electrode in the first insulating region, a contact wiring, a first wiring layer electrically connecting the contact wiring and the first transistor, and a first junction region electrically connected to the first wiring layer. The second semiconductor layer includes a second transistor having second source or drain regions in the second semiconductor region and a second gate electrode in the second insulating region, a second wiring layer electrically connecting the contact wiring and the second transistor, and a second junction region electrically connected to the second wiring layer.