Stacked Image Sensor Landing Structure for Lower Parasitic Capacitance
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Solution Overview
Problem
Current image sensors face challenges in achieving high integration density and improved electrical characteristics, such as increased parasitic capacitance and reduced degree of freedom in wiring, which affect their performance.
Innovation Solution
The proposed image sensor architecture involves a multilayer chip structure with specific bonding and wiring configurations, including a landing structure made of the same material as the gate electrodes, and a unique bonding via arrangement that reduces parasitic capacitance and enhances integration density and electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional image sensor architecture is used, then manufacturing is simpler, but integration density is lower and parasitic capacitance is higher
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional wiring by introducing vertical vias and stacked chip structures. The bonding vias extend vertically through multiple chip layers, enabling electrical connections in the depth dimension rather than only in the plane, thereby increasing integration density without proportionally increasing wiring complexity.
Solution Approach 2:
The patent implements a stacked chip architecture where multiple chip structures are nested vertically. Each chip contains circuit devices and wiring, and chips are bonded together through bonding vias and bonding pads, creating a nested configuration that increases integration density by utilizing vertical space.
2Reliability
If conventional wiring configuration is used, then manufacturing is easier, but parasitic capacitance is higher
Solution Approach 1:
The patent divides the wiring structure into segmented components: bonding vias, bonding pads, and inter-chip connections. This segmentation allows each component to be optimized independently for electrical performance while managing manufacturing complexity through modular fabrication processes.
Solution Approach 2:
The patent applies different material properties and structural characteristics to different regions of the wiring structure. For example, bonding vias use specific materials with low resistivity, while bonding pads are designed with larger surface areas for optimal electrical contact, thereby improving overall electrical characteristics without uniform complexity throughout.
3Reliability
If bonding via penetrates through entire substrate, then electrical connection is better, but parasitic capacitance increases
Solution Approach 1:
The patent extracts the bonding via structure from penetrating the entire substrate thickness. Instead, bonding vias are configured to extend only to the necessary depth to establish electrical connections between bonding pads on different chips, removing the unnecessary portion that would contribute to parasitic capacitance while maintaining reliable electrical connection.
Data Source
AI summary
An image sensor includes a lower substrate having a first surface and a second surface opposing the first surface, lower circuit devices disposed on the first surface, a lower wiring structure electrically connected to the lower circuit devices on the first surface, a lower bonding pad on the second surface, a lower bonding via penetrating through the lower substrate between the lower bonding pad and the lower wiring structure, a landing structure disposed on the first surface and contacting the lower bonding via, an upper bonding pad bonded to the lower bonding pad on the lower bonding pad, and an upper substrate disposed on the upper bonding pad and including photoelectric conversion devices. At least a portion of the landing structure horizontally overlaps the lower circuit devices.