CMOS Image Sensor Light Shielding for Global Shutter Signal Integrity
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Solution Overview
Problem
Current image sensors with global shutters face challenges in capturing fast-moving objects due to limitations in the design and operation of pixel units, particularly in the transfer and storage of image charges, which can lead to signal mixing and loss during the exposure and readout processes.
Innovation Solution
The design incorporates a CMOS image sensor with a global shutter, featuring a shutter gate transistor, a photosensitive device, a storage device, and a driving circuit, where the storage device includes a P-N junction and a light shielding element to prevent signal loss by shielding the storage node from incident light, and the driving circuit facilitates the transfer and readout of image charges efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a memory element is added to each pixel for global shutter function, then the ability to capture fast-moving objects is improved, but the device complexity increases
Solution Approach 1:
The patent combines the memory element, photodiode, and readout circuitry into an integrated pixel unit structure. The transfer gate transistor connects the photodiode to the memory element, enabling seamless charge transfer while maintaining a compact design that reduces overall system complexity despite adding global shutter functionality.
Solution Approach 2:
The pixel unit is designed with multi-functional components that serve multiple purposes. The memory element not only stores photo-generated charges but also enables the global shutter function for capturing fast-moving objects. The transfer gate transistor facilitates both charge transfer during normal operation and charge isolation during shutter operation, providing universal functionality across different operating modes.
2Reliability
If the storage device stores photo-generated charges, then the global shutter function is enabled, but signal mixing and loss occur during transfer and readout
Solution Approach 1:
The transfer gate transistor serves as an intermediary between the photodiode and the memory element. It controls the transfer of photo-generated charges with high precision, minimizing signal loss during the transfer process. The gate structure allows selective charge transfer while isolating the stored charges from interference, maintaining signal integrity throughout the readout process.
3Measurement precision
If the pixel unit captures image charges efficiently, then the readout accuracy is improved, but the susceptibility to incident light interference increases
Solution Approach 1:
The patent extracts the storage node from direct exposure to incident light by positioning it beneath the photosensitive device and transfer gate structures. The memory element is designed to receive and store charges indirectly through the transfer gate, isolating the storage function from the photosensitive function. This separation prevents incident light from directly interfering with the stored charges while maintaining accurate charge transfer and readout capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables accurate and efficient capture of image charges, preventing signal mixing and loss, and allows for reliable readout of image data from fast-moving objects by ensuring the storage of charges without interference from incident light.
Implementation Method 1
The memory element is configured to temporarily store photo-generated charges
Implementation Method 2
a light shielding element to prevent signal loss by shielding the storage node from incident light
Data Source
AI summary
An image sensor includes a storage device, where the storage device includes a memory element, a first dielectric layer and a light shielding element. The memory element includes a storage node and a storage transistor gate, where the storage transistor gate is located over the storage node. The first dielectric layer is located over a portion of the storage transistor gate. The light shielding element is located on the first dielectric layer and includes a semiconductor layer. The semiconductor layer is electrically isolated from the memory element, where the light shielding element is overlapped with at least a part of a perimeter of the storage transistor gate in a vertical projection on a plane along a stacking direction of the memory element and the light shielding element, and the stacking direction is normal to the plane.