Image Sensor Logic Block Adjusts Slew Rates to Stabilize Power
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Solution Overview
Problem
Conventional image sensing devices face issues with voltage drops in power source voltage, leading to delayed decision timings and erroneous count signals due to shared power source usage across comparison and storing blocks, affecting operational reliability.
Innovation Solution
The introduction of a logic block that adjusts the slew rates of comparison signals and delays their deactivation edges, allowing the comparison and storing blocks to operate using the same source voltage while minimizing the impact of voltage drops by generating logic signals with adjusted slew rates and using them to latch count signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the comparison block and storing block share the same power source voltage, then device complexity is reduced, but voltage drops cause delayed decision timings and erroneous count signals
Solution Approach 1:
The patent divides the power source usage into two segments: the comparison block uses a first power source voltage (VDD) while the storing block uses a second power source voltage (VDDA). This segmentation allows independent power supply management, preventing voltage drops in one block from affecting the other, thus maintaining operational reliability while keeping the power source configuration manageable.
Solution Approach 2:
The patent introduces an intermediary mechanism through the logic block that generates control signals based on comparison results. This logic block acts as a mediator that processes signals from the comparison block and triggers the storing block at appropriate times, ensuring accurate count signal latching even when power source voltages differ and drop characteristics vary.
2Productivity
If multiple blocks operate simultaneously using the same power source, then productivity is improved, but voltage drops lead to measurement errors in count signals
Solution Approach 1:
The patent segments the power supply into distinct channels for different functional blocks. The comparison block operates on VDD while the storing block operates on VDDA, allowing simultaneous operation without mutual interference from voltage drops. This ensures that count signal measurement precision is maintained even during high-productivity simultaneous operations.
Solution Approach 2:
The patent implements a feedback mechanism where the logic block monitors comparison signals and generates appropriate control signals to trigger the storing block. This feedback ensures that count signals are latched at the correct decision timing, maintaining measurement precision even when multiple blocks operate simultaneously with different power source characteristics.
3Reliability
If the decision timing is delayed due to voltage drops, then operational reliability deteriorates, but adding separate power sources increases device complexity
Solution Approach 1:
The patent segments the power source configuration into two independent voltage supplies (VDD and VDDA) for the comparison and storing blocks respectively. This segmentation prevents voltage drops in one block from causing decision timing delays in another, maintaining reliability without requiring complex voltage regulation or timing compensation circuits.
Solution Approach 2:
The logic block serves as an intermediary that receives comparison signals from the comparison block and generates control signals for the storing block. This intermediary ensures that decision timing is accurately captured and transferred, preventing delays caused by voltage drops from affecting the overall timing accuracy of the system.
Data Source
AI summary
An image sensing device includes: a pixel array suitable for generating a plurality of pixel signals corresponding to incident light; a comparison block suitable for comparing the pixel signals with a ramp signal to generate a plurality of comparison signals; a logic block suitable for adjusting slew rates of the respective comparison signals to generate a plurality of logic signals; a global count block suitable for generating a global count signal; and a storing block suitable for storing counted values of the global count signal based on the logic signals received from the logic block.