Image Sensor Package Thickness Reduction via Metal Interconnect
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Solution Overview
Problem
Conventional image sensor integrated circuit packages are bulky due to the presence of a printed circuit board, which occupies valuable space in electronic devices and makes handling cumbersome.
Innovation Solution
The solution involves mounting the image sensor die to a thin metal interconnect layer on a sacrificial carrier substrate, which is then selectively removed to expose the metal interconnects, allowing for a reduced thickness package configuration, such as a ball grid array or leadless chip package, by using wire bonds or flip-chip mounting techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a printed circuit board is used in the image sensor package, then electrical connectivity and structural support are provided, but the package thickness increases and space is consumed
Solution Approach 1:
The patent extracts and removes the printed circuit board from the image sensor package, retaining only the essential metal interconnect layer that provides electrical connectivity. This eliminates the bulky PCB structure while preserving the necessary electrical functions through direct mounting of the image sensor die to the thin metal interconnect layer.
Solution Approach 2:
The patent employs a thin metal interconnect layer as a replacement for the thick printed circuit board. This thin film structure provides the necessary electrical connectivity and structural support while dramatically reducing the package thickness and overall size of the image sensor assembly.
2Stability of the object's composition
If a printed circuit board is used in the image sensor package, then structural support is provided, but handling becomes cumbersome and space efficiency decreases
Solution Approach 1:
The patent removes the excessive structural support provided by the printed circuit board, retaining only the minimal necessary support from the metal interconnect layer and carrier substrate. This extraction of unnecessary structural elements reduces the overall package size and improves handling ease while maintaining sufficient structural integrity for the image sensor die.
3Reliability
If a printed circuit board is used in the image sensor package, then electrical connectivity is established, but valuable real estate in the electronic device is consumed
Solution Approach 1:
The patent extracts the printed circuit board from the package structure, removing the source of excessive space occupancy. The essential electrical connectivity functions are preserved through the retained metal interconnect layer, which occupies minimal space compared to the full PCB structure, thereby freeing up valuable real estate in the electronic device.
Solution Approach 2:
The patent transitions from a planar PCB-based structure to a three-dimensional stacked configuration where the image sensor die is mounted directly on the thin metal interconnect layer. This dimensional reorganization eliminates the need for lateral space expansion and allows for compact integration within the electronic device footprint.
Data Source
AI summary
An image sensor die may include a pixel array formed in an image sensor substrate. The image sensor die may be mounted to a thin metal interconnect layer that has been deposited on a sacrificial carrier substrate. The thin metal interconnect layer may include one or more metal layers that are patterned to form metal traces that serve as contact pads, signal lines, and other interconnects in the interconnect layer. The image sensor die may be wire bonded, flip-chip mounted, or otherwise mechanically and electrically coupled to the metal interconnect layer. The sacrificial carrier substrate may be etched or otherwise removed to expose the metal interconnects on the metal interconnect layer. An array of solder balls may be formed on the exposed metal interconnects to form a ball grid array package, or the exposed contact pads may be plated to form a leadless chip carrier package.


