Solid-State Image Sensor Negative Capacitance Circuit
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Solution Overview
Problem
Solid-state image sensors face challenges in reducing parasitic capacitance on vertical signal lines, which increases settling time and affects readout speed, and existing solutions like current mirror circuits introduce noise and require material and process improvements.
Innovation Solution
Incorporating a negative capacitance circuit connected to the vertical signal lines, which includes an amplifier and capacitor to reduce line capacitance, and optionally using a current source and transistors in cascode configuration to manage bias voltages and control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a current mirror circuit is connected to the vertical signal line to supply compensating current, then the settling time is shortened and readout speed is improved, but noise increases and signal quality deteriorates
Solution Approach 1:
The patent extracts and removes the problematic current mirror circuit from the system. Instead of using active compensation circuits that generate noise, the invention eliminates the root cause by reducing the line capacitance itself through material improvements and structural optimization of the vertical signal lines, thereby achieving fast readout without noise contamination
Solution Approach 2:
The patent changes the physical parameters of the vertical signal lines by improving materials and manufacturing processes to reduce line capacitance. This parameter change allows the system to achieve fast settling times without requiring additional active compensation circuits, thus avoiding noise generation
2Object-generated harmful factors
If the line capacitance of vertical signal lines is reduced by improving materials and manufacturing processes, then the need for current mirror circuits is eliminated and signal quality is maintained, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by incorporating noise prevention measures directly into the manufacturing process. By improving materials and processes upfront to reduce line capacitance, the design eliminates the need for subsequent noise mitigation circuits, achieving both signal quality and manufacturing efficiency
3Object-generated harmful factors
If the line capacitance is reduced to eliminate current mirror circuits, then noise is reduced and signal quality is maintained, but settling time may be affected
Solution Approach 1:
The patent changes the capacitance parameter of the vertical signal lines by improving materials and manufacturing processes. This reduction in line capacitance simultaneously achieves both goals: eliminating noise from current mirror circuits and reducing settling time, as lower capacitance allows faster charging and discharging of the signal lines
Data Source
AI summary
It makes it easier to reduce the line capacitance of vertical signal lines in a solid-state image sensor in which signals are output via the vertical signal lines.The solid-state image sensor is provided with a logic circuit, a pixel circuit, and a negative capacitance circuit. In the solid-state image sensor, the logic circuit processes an analog signal. Also, in the solid-state image sensor, the pixel circuit generates an analog signal by photoelectric conversion, and outputs the analog signal to the logic circuit via a predetermined signal line. In the solid-state image sensor, the negative capacitance circuit is connected to the predetermined signal line.