Stacked Image Sensor Shielding for Logic Noise Isolation
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Solution Overview
Problem
Existing image sensors face challenges in achieving improved electrical reliability, particularly due to interference from electrical noise generated by logic devices in adjacent semiconductor chips.
Innovation Solution
The image sensor design incorporates a shielding structure layer with a shielding metal pattern buried in the back side insulating layer, along with a conductive through-via and a bonding layer to connect the semiconductor chips, thereby reducing electromagnetic interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor chips are stacked together to form an image sensor, then integration density and functionality are improved, but electrical noise interference between chips increases
Solution Approach 1:
A shielding structure layer comprising a shielding metal pattern is introduced as an intermediary between the first semiconductor chip (containing pixels) and the third semiconductor chip (containing logic devices). This shielding layer acts as a mediator that blocks electrical noise generated by the logic devices from interfering with the pixel circuits, while allowing the multi-chip stacking integration to proceed.
Solution Approach 2:
The harmful electrical noise generated by the logic devices in the third semiconductor chip is extracted and blocked by the shielding structure layer. The shielding metal pattern is specifically positioned to intercept and contain the electrical noise, preventing it from reaching the sensitive pixel circuits in the first semiconductor chip.
2Reliability
If a shielding structure layer is added to reduce electrical noise, then electrical reliability is improved, but device complexity increases
Solution Approach 1:
The shielding structure layer is applied locally only in the region where electrical noise interference occurs between the first and third semiconductor chips. The shielding metal pattern is positioned specifically over the pixel circuit region, providing targeted noise protection without requiring comprehensive shielding throughout the entire device, thus limiting the increase in complexity to only the necessary areas.
3Reliability
If bonding layers and connection patterns are added to connect multiple chips, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The bonding layer serves multiple functions simultaneously: it provides mechanical bonding between the first and second semiconductor chips, establishes electrical connectivity through the connection patterns, and integrates the shielding structure layer into the overall assembly. By combining these functions into a single integrated layer, the number of separate manufacturing steps is reduced.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the electrical reliability of the image sensor by effectively shielding the pixel signal generator circuit from electrical noise, leading to improved performance and reduced noise interference.
Implementation Method 1
a shielding structure layer including a shielding metal pattern on the first back side insulating layer
Data Source
AI summary
An image sensor includes a first semiconductor chip including a first semiconductor substrate including a plurality of pixels and a first wiring structure having a first bonding pad; a second semiconductor chip including a second semiconductor substrate having pixel signal generator circuits, a second wiring structure on the second semiconductor substrate and having an upper bonding pad bonded to the first bonding pad, a back side insulating layer on a lower surface of the second semiconductor substrate and including a shielding metal pattern buried therein, and a conductive through-via penetrating the back side insulating layer and the first semiconductor substrate, and a third semiconductor chip including a bonding layer having a lower bonding pad connected to the conductive through via, a third semiconductor substrate including logic devices, and a third wiring structure having a third bonding pad bonded to the lower bonding pad.