Image Sensor Package with Air Gaps and Elastic Build-up Layers
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Solution Overview
Problem
Conventional semiconductor packaging techniques for CMOS image sensors are expensive, difficult to manufacture, and suffer from poor thermal dissipation and mechanical stress issues due to CTE mismatching, leading to performance limitations in high-density, compact devices.
Innovation Solution
A package-on-package (PoP) structure with a multi-chip configuration, featuring air gaps and lead-free solder balls/bumps, elastic build-up layers for stress absorption, and a transparency material for improved thermal and mechanical performance, along with a flexible printed circuit board and IR filter for enhanced electrical and thermal dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional housing assembly packaging is used for CMOS image sensors, then the sensor is protected from damage, but the manufacturing cost increases and manufacturing difficulty increases
Solution Approach 1:
The patent combines the sensor chip, lens array, and housing assembly into an integrated module. The lens array is directly mounted on the sensor chip surface, and the housing encloses both components as a single unit, eliminating separate packaging steps and reducing manufacturing complexity while maintaining protection.
Solution Approach 2:
The patent implements a nested structure where the lens array is positioned on top of the sensor chip, which is mounted on the substrate, all enclosed within the housing. This nested arrangement maximizes space utilization and integrates multiple functions into a compact package, reducing overall manufacturing steps.
2Reliability
If conventional leaded solder materials are used for connecting chips, then electrical connection is achieved, but thermal dissipation performance deteriorates and manufacturing precision is reduced due to lead-free requirements
Solution Approach 1:
The patent uses composite solder materials containing silver particles dispersed in the solder matrix. This composite structure enhances thermal conductivity while maintaining electrical connection, allowing effective heat dissipation from the chip to the substrate without compromising joint reliability.
Solution Approach 2:
The patent applies different material compositions to different regions: the solder joints use composite materials with enhanced thermal properties, while other structural areas use conventional materials. This localized optimization improves thermal management at critical heat generation points without affecting overall manufacturing precision.
3Volume of moving object
If chips are densely packed to reduce device size, then device dimension is reduced, but thermal dissipation performance deteriorates due to confined heat spreading
Solution Approach 1:
The patent introduces thermally conductive adhesive materials as intermediaries between the chip and substrate, and between adjacent chips. These adhesive layers serve as thermal pathways that conduct heat away from densely packed chips, enabling effective heat spreading in compact configurations without compromising thermal performance.
Solution Approach 2:
The patent replaces conventional mechanical thermal management structures with material-based thermal conduction solutions. Instead of adding complex heat sinks or cooling mechanisms, the patent uses thermally conductive adhesive materials to passively conduct heat away from chips, achieving thermal management in a space-efficient manner.
4Ease of manufacture
If CTE mismatching between different materials is not addressed, then manufacturing is simpler, but mechanical stress increases leading to reliability issues
Solution Approach 1:
The patent selects materials with matched coefficients of thermal expansion (CTE) for components that are thermally coupled, such as the chip, substrate, and housing. This parameter matching minimizes thermal stress during temperature cycling, preventing delamination and cracking while maintaining manufacturing simplicity.
Solution Approach 2:
The patent uses composite adhesive materials that can accommodate CTE differences between dissimilar materials. These adhesives have viscoelastic properties that allow them to absorb thermal expansion mismatches, reducing mechanical stress at interfaces without complicating the manufacturing process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a cost-effective, high-performance, and reliable semiconductor package with improved thermal dissipation and mechanical stability, enabling better device performance and reliability through efficient stress management and efficient heat spreading.
Implementation Method 1
An air gap is created between the first package and the second package
Implementation Method 2
An air gap is created between the first package and the second package
Implementation Method 3
solder balls/bumps formed under the second package
Implementation Method 4
elastic build-up layers for stress absorption
Implementation Method 5
a transparency material for improved thermal and mechanical performance
Implementation Method 6
a flexible printed circuit board for enhanced electrical and thermal dissipation
Data Source
AI summary
An image sensor multi-chips package structure, includes a first package including a first chip with image sensors having first bonding pads and micro lens on a first active surface, a first die receiving window and first conductive inter-connecting through holes penetrated from a first upper contact pads on a first upper surface of the first chip to a first lower contact pads on a first lower surface of the first chip, wherein a first upper build up layer on the active surface of the first chip coupling from the first bonding pads to the first upper contact pads; a second package comprising a second chip having second bonding pads on a second active surface, a second die receiving window and second conductive inter-connecting through holes penetrated from a second upper contact pads of a second upper surface of the second chip to a second lower contact pads on a second lower surface of the second chip, wherein a second upper build up layers on the second upper surface for coupling from the second bonding pads to the second upper contact pads, and second lower build up layers under the second lower surface for coupling from the second lower contact pads to terminal pads located under the second lower surface; and inter-connecting structures coupled between the first lower contact pads to the second upper contact pads.