3D Image Sensor Pixel Stacking via Concavo-Convex Pad Alignment
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Solution Overview
Problem
Conventional methods for aligning wafers in image sensor manufacturing face challenges with precision and uniformity, particularly in the TSV process, and require separate devices or techniques like infrared irradiation and laser punching, which can degrade alignment precision.
Innovation Solution
A three-dimensional unit pixel structure is developed, where one chip has projecting pads and the other has corresponding depressed pads forming a concavo-convex structure, allowing for precise alignment and bonding without additional alignment devices, using thermal energy to bond the pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSV process is used for wafer alignment, then electrical connection between top and bottom wafers is achieved, but manufacturing precision deteriorates due to difficulty in etching and filling high aspect ratio vias
Solution Approach 1:
The patent extracts the alignment function from the TSV structure itself and relocates it to separate alignment marks formed on the wafer surfaces. This allows the TSV to focus solely on electrical connection while the alignment marks handle positioning, resolving the conflict between electrical connection reliability and manufacturing precision.
Solution Approach 2:
The patent segments the TSV structure into two independent functions: alignment marks for positioning and TSV for electrical connection. By separating these functions into distinct structural elements, the patent eliminates the interference between etching/filling difficulties and alignment precision requirements.
2Manufacturing precision
If infrared irradiation or laser punching is used for wafer alignment, then alignment is achieved, but device complexity increases due to requirement of separate alignment devices
Solution Approach 1:
The patent implements self-service alignment where the wafer structure itself provides the alignment functionality through integrated alignment marks. This eliminates the need for external infrared irradiation devices or laser punching equipment, reducing device complexity while maintaining alignment precision.
Solution Approach 2:
The patent merges the alignment function into the wafer structure by forming alignment marks directly on the wafer during the manufacturing process. This integration combines the wafer substrate and alignment reference into a single system, eliminating separate alignment devices.
3Reliability
If through-silicon vias with high aspect ratio are used, then electrical connection between stacked chips is achieved, but ease of manufacture deteriorates due to difficulty in etching and filling
Solution Approach 1:
The patent extracts the alignment function from the TSV structure and places it in separate alignment marks. This allows the TSV to be optimized solely for electrical connection with appropriate dimensions, while the alignment marks handle positioning, making the overall manufacturing process easier.
Solution Approach 2:
The patent performs preliminary formation of alignment marks before TSV etching and filling processes. This preliminary action provides a reference framework that guides subsequent manufacturing steps, making the complex TSV process more manageable and easier to execute with consistent results.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables easy and precise alignment of chips during image sensor manufacturing, reducing the need for separate alignment tools and improving manufacturing efficiency and cost-effectiveness.
Implementation Method 1
using thermal energy to bond the pads
Data Source
AI summary
A unit pixel of an image sensor having a three-dimensional structure includes a first chip and a second chip which are stacked, one of the first chip and the second chip having a photodiode, and the other of the first chip and the second chip having a circuit for receiving information from the photodiode and outputting received information. The first chip includes a first pad which is projectedly disposed on an upper surface of the first chip in such a way as to define a concavo-convex structure, and the second chip includes a second pad which is depressedly disposed on an upper surface of the second chip in such a way as to define a concavo-convex structure corresponding to the concavo-convex structure of the first chip. The first chip and the second chip are mated with each other through bonding of the first pad and the second pad.