Back-Side Image Sensor Pad Layout for Planar BCFA Surfaces
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Solution Overview
Problem
The integration of a buried color filter array (BCFA) with existing CMOS image sensor processes is challenging due to the requirement of a substantially planar light-receiving surface, which is often disrupted by scribe line openings, leading to passivation layer damage and compromised optical performance.
Innovation Solution
A method is introduced where a flat pad structure is formed within the scribe line opening, followed by a planarization process, allowing the passivation layer to be formed after the pad and dielectric layer formation, thereby eliminating damage and ensuring a smooth surface for the BCFA process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If scribe line openings are formed in the semiconductor substrate, then the substrate can be divided into separate devices for packaging and testing, but the light-receiving surface becomes non-planar causing passivation layer damage and reduced optical performance
Solution Approach 1:
The pad structure is formed within the scribe line opening before the passivation layer is deposited. This preliminary formation of the pad structure ensures that when the passivation layer is subsequently deposited, it can conform to the underlying features and maintain planarity across the light-receiving surface, preventing passivation layer damage while still allowing device separation.
2Device complexity
If the passivation layer is formed before the pad structure, then the manufacturing process is simpler, but the passivation layer becomes damaged and optical performance is compromised
Solution Approach 1:
The pad structure is formed in advance within the scribe line opening before the passivation layer deposition. This sequencing ensures the passivation layer is deposited over a stable, pre-formed structure, preventing damage to the passivation layer and maintaining its integrity for optimal optical performance.
Solution Approach 2:
The scribe line opening is segmented into distinct functional zones: the pad structure confined to the opening and the light-receiving surface adjacent to it. This segmentation allows the pad to be formed without interfering with the planarity of the light-receiving surface, enabling the passivation layer to maintain integrity across both regions.
3Ease of operation
If the pad structure protrudes above the semiconductor substrate surface, then electrical connections are easier to make, but the surface becomes non-planar disrupting the BCFA process
Solution Approach 1:
The pad structure is localized within the scribe line opening, which is positioned away from the light-receiving surface. This local confinement allows the pad to have a different geometry (protruding for electrical connection) without affecting the planarity of the light-receiving surface, thus satisfying both electrical connection requirements and BCFA process requirements.
Solution Approach 2:
The pad structure utilizes the vertical dimension by protruding above the substrate surface within the scribe line opening, providing accessible electrical connection points. Simultaneously, the light-receiving surface maintains its planarity in the horizontal plane, allowing the BCFA process to proceed without disruption. This dimensional separation resolves the contradiction between connection accessibility and surface planarity.
Data Source
AI summary
A semiconductor structure includes: a semiconductor substrate arranged over a back end of line (BEOL) metallization stack, and including a scribe line opening; a conductive pad having an upper surface that is substantially flush with an upper surface of the semiconductor substrate, the conductive pad including an upper conductive region and a lower conductive region, the upper conductive region being confined to the scribe line opening substantially from the upper surface of the semiconductor substrate to a bottom of the scribe line opening, and the lower conductive region protruding downward from the upper conductive region, through the BEOL metallization stack; a passivation layer arranged over the semiconductor substrate; and an array of pixel sensors arranged in the semiconductor substrate adjacent to the conductive pad.