Image Sensor Driver Circuit With Selectable Parallel FET Stages
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Solution Overview
Problem
Existing driving devices for solid-state image pickup devices, such as CCDs, require a large number of control lines or configuration values to change the driving capability, leading to increased complexity and component count, which hinders efficient control of the driving signals.
Innovation Solution
A driving device with a control circuit that produces control signals to selectively operate a series of FETs in parallel, allowing for the arbitrary change of the number of FETs driven using a small number of control signals, with each FET connected in complementary pairs to produce driving signals with adjustable voltage levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large number of control lines are used to control each 3-state buffer individually, then the driving capability can be adjusted, but the device complexity increases
Solution Approach 1:
Multiple control lines are merged into a single control line by encoding the control signals. Instead of having separate control lines for each 3-state buffer, the invention combines the control functions into one line that can selectively enable or disable groups of buffers through encoded control signals, thereby reducing the total number of control lines while maintaining the ability to adjust driving capability.
Solution Approach 2:
The single control line serves multiple functions by encoding different control patterns. It can selectively control different numbers of 3-state buffers (e.g., 1, 2, 4, or 8 buffers) depending on the encoded control signal, making the control line universal for multiple control purposes rather than requiring dedicated lines for each function.
2Adaptability or versatility
If multiple OR gates and AND gates are connected in parallel to increase switching stages, then the driving capability can be switched at more stages, but the component count increases
Solution Approach 1:
The invention merges the control logic of multiple OR gates and AND gates into a simplified control structure. Instead of having separate OR and AND gates for each switching stage, the control signals are processed through a unified decoding mechanism that directly controls the 3-state buffers, eliminating the need for multiple gate structures while achieving the same multi-stage switching capability.
Solution Approach 2:
The invention extracts the essential control function from the complex OR-AND gate structure and implements it through a simpler decoding logic. The complex gate structures are removed, and only the necessary control decoding circuitry is retained, reducing the component count while preserving the multi-stage switching functionality.
3Manufacturing precision
If configuration values are set for each structure including OR gate, AND gate, transistors, then the driving capability can be precisely controlled, but a lot of configuration values are required
Solution Approach 1:
Multiple configuration values are merged into a single encoded control signal. Instead of requiring separate configuration values for each OR gate, AND gate, and transistor, the invention combines all these control parameters into one encoded control signal that simultaneously sets the state of multiple components, thereby reducing the total number of configuration values needed while maintaining precise control over the driving capability.
4Device complexity
If a small number of control signals are used to selectively operate FETs in parallel, then the device complexity is reduced, but the ability to arbitrarily change the number of FETs driven is limited
Solution Approach 1:
The control system is made dynamic by using encoded control signals that can represent multiple states. A single control line can dynamically switch between different control patterns (e.g., controlling 1, 2, 4, or 8 FETs) depending on the encoded signal, allowing arbitrary changes in the number of driven FETs without increasing the number of control lines, thus maintaining adaptability while reducing complexity.
Data Source
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AI summary
A driving circuit includes first through N-th selective operation driving portions selectively producing first through N-th selective operation driving signals, a selection circuit selectively driving the first through the N-th selective operation driving portions in response to an input signal and a control signal, and a supplying arrangement combining the first through the N-th selective operation driving signals to supply a combined driving signal to a solid-stage image pickup device. An n-th selective operation riving portion includes (M x 2(n-1)) P-charmel FETs connected in parallel with each other and (M × 2(n-1)) N-channel FETs connected in parallel with each other. The (M × 2 (n-1)) P-channel FETs have drains connected to drains of the (M × 2(n-1)) N-channel FETs.