Image Sensor Parallel Readout Architecture for High Frame Rate
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Solution Overview
Problem
Traditional image sensors using electronic rolling shutter (ERS) algorithms are limited by their ability to process signals for a single row of pixels at a time, which restricts maximum frame rates and resolution, and are susceptible to manufacturing defects, leading to poor image capture in low-light environments and increased production costs.
Innovation Solution
Implementing a rolling global shutter (RGS) technology that allows for the simultaneous reset and readout of multiple rows of pixels, using configurable binning and redundant output stages to enhance signal-to-noise ratio and reduce manufacturing defects, thereby improving frame rates and resolution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional electronic rolling shutter algorithm is used to process single row of pixels at a time, then device complexity is reduced, but frame rate and resolution are limited
Solution Approach 1:
The pixel array is divided into multiple independent row groups, each with its own dedicated pixel output stage. This segmentation allows parallel processing of multiple rows simultaneously, increasing frame rate without requiring a single complex output stage to handle all rows sequentially.
Solution Approach 2:
The patent transitions from single-row sequential processing to multi-row parallel processing by adding the row dimension to the processing architecture. Multiple pixel output stages operate simultaneously on different rows, effectively moving from a one-dimensional sequential approach to a two-dimensional parallel approach.
2Productivity
If row integration period is reduced to achieve higher frame rates, then frame rate is improved, but image capture quality in low-light environments deteriorates
Solution Approach 1:
Multiple rows are integrated simultaneously over the same exposure period, ensuring continuous and uninterrupted light capture across the entire active region. This parallel integration maintains full exposure time for each pixel while increasing the overall frame rate through simultaneous readout of multiple rows.
3Reliability
If manufacturing defects occur in processing data-paths, then operational resolution and frame rate are limited, but implementing redundancy increases device complexity
Solution Approach 1:
Redundant pixel output stages are pre-configured and integrated into the sensor architecture before operation. During manufacturing and initial operation, the system automatically identifies functional output stages and configures the row groups to utilize only operational stages, preventing defects from limiting overall performance.
Solution Approach 2:
The system dynamically reconfigures the mapping between row groups and pixel output stages based on the operational status of each stage. When defects are detected, the parameters of the system are changed to route rows through functional output stages, maintaining optimal resolution and frame rate despite manufacturing variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The RGS technology enables higher frame rates and improved image quality by processing multiple rows in parallel, reducing noise and manufacturing defects, and allowing for better low-light performance and reduced production costs.
Implementation Method 1
Each pixel receives incident photons (light) and converts the photons into electrical signals
Data Source
AI summary
An image sensor configured to readout an arbitrary number of rows in parallel is described, comprising a rolling global shutter pixel array which can be operated as a true global shutter. Shielding structures may be formed in the pixel array to minimize signal coupling between adjacent pixels when multiple rows are simultaneously reset and read out. A plurality of column select lines may be formed in a given pixel pitch, and the image sensor may utilize read out components and circuitry associated with conventional readout circuits to be used in simultaneously reading out a two-dimensional region of the image sensor. The image sensor may be configured to use charge binning between rows that are reset and read out in parallel to improve power consumption. The image sensor may include redundant output stages with routing circuitry that improves image sensor yield by compensating for yield loss in the output stage.